Patterning strategy and performance of 1.3NA tool for 32nm node lithography

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6924, Issue , 2008, Pages

  Mimotogi, Shoji ^a   Satake, Masaki ^a   Kitamura, Yosuke ^a   Takahata, Kazuhiro ^a   Kodera, Katsuyoshi ^a   Fujise, Hiroharu ^a   Ema, Tatsuhiko ^a   Sho, Koutaro ^a   Ishigo, Kazutaka ^a   Kono, Takuya ^a   Asano, Masafumi ^a   Yoshida, Kenji ^a   Kanai, Hideki ^a   Kyoh, Suigen ^a   Harakawa, Hideaki ^a   Nomachi, Akiko ^a   Ishida, Tatsuya ^b   Miyashita, Katsura ^a   Inoue, Soichi ^a  

^a TOSHIBA CORPORATION   (Japan)

^b Semiconductor Company   (Japan)

Author keywords

32nm node; Dose focus budget; Low k1 lithography; Single exposure

Indexed keywords

LOGIC DEVICES; NANOTECHNOLOGY; SODIUM;

CONTACT HOLE (CH); EXPERIMENTAL RESULTS; HIGH DENSITY SRAM; LINE PATTERNING; LITHOGRAPHY PROCESSES; OPTICAL MICRO LITHOGRAPHY; SINGLE EXPOSURE;

LITHOGRAPHY;

EID: 45449100537     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.772201     Document Type: Conference Paper

References (7)

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3. S.Mimotogi et al., "Performance of Immersion Lithography for 45nm-node CMOS and Ultra-High Density SRAM with 0.25um2", SPIE Vol.6520-8(2007)
4. Kohji Hashimoto et al., "ArF Lithography Technologies for 65nm-node CMOS (CMOS5) with 30nm Logic Gate and High Density Embedded Memories", Proc. of VLSI symposium 2003,4B-2
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6. T.Ema, "Immersion resist process for 32-nm node logic devices", SPIE Vol.6923-13(2008)
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