A single-poly EEPROM cell for embedded memory applications

Solid-State Electronics

Volumn 53, Issue 6, 2009, Pages 644-648

  Di Bartolomeo, A ^a,b   Rucker H ^a   Schley, P ^a   Fox, A ^a   Lischke, S ^a   Na, Kee Yeol ^a,c  

^a IHP   (Germany)

^b INFN SEZIONE DI ROMA   (Italy)

^c Chungbuk Provincial College   (South Korea)

Author keywords

Data retention; EEPROM; Endurance; Flash memory; Fowler Nordheim tunnelling; Non volatile memory; Reliability; Single poly silicon

Indexed keywords

DATA RETENTION; EEPROM; ENDURANCE; FOWLER-NORDHEIM TUNNELLING; NON-VOLATILE MEMORY; SINGLE-POLY-SILICON;

CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; DURABILITY; MOS CAPACITORS; POLYSILICON; ROM; SEMICONDUCTING SILICON; TUNERS; TUNNELING (EXCAVATION);

FLASH MEMORY;

EID: 65549166346     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2009.04.007     Document Type: Article

References (22)

1. Ohsaki K., Asamoto N., and Takagaki S. A single poly EEPROM cell structure for use in standard CMOS processes. IEEE J Solid State Circ 29 3 (1994) 311-316
2. Baldi L., Cascella A., and Vajana B. A scalable single poly EEPROM cell for embedded memory applications. Microelectron J 28 (1997) 657-661
3. McPartland RJ, Singh R. 1.25 V, low-cost, embedded FLASH memory for low-density applications. In: Symposium on VLSI circuits. Digest of technical paper; 2000. p. 158-61.
4. Carman E, Parris P, Chaffai H, Cotdeloup F, Debortoii S, Hemon E, et al. Single poly EEPROM for smart power IC's. In: Proceedings of the 12th international symposium on power semiconductor devices and IC's; 2000. p. 177-9.
5. Shalchian M, Atarodi SM. A logic CMOS compatible flash EEPROM for small scale integration. In: Proceedings of the 15th international conference on microelectronics, ICM 2003; 2003. p. 348-51.
6. Vega-Castillo P, Krautschneider W. Single poly PMOS-based CMOS compatible low voltage OTP. In: Proceedings of SPIE, the international society for optical engineering, VLSI circuits and systems. Conference No. 2, vol. 5837; 2005. p. 953-60.
7. Ren T, Pan L, Liu Z, Zhu J. A novel single poly EEPROM cell structure on thin oxide tunnel technology. In: Proceedings of 7th international conference on solid-state and integrated circuits technology, vol. 1; 2004. p. 711-3.
8. Lin C.F., and Sun C.Y. A single-poly EEPROM cell structure compatible to standard CMOS process. Solid State Electron 51 (2007) 888-893
9. Rücker H, Heinemann B, Barth R, Bauer J, Blum K, Bolze D, et al. SiGe BiCMOS technology with 3.0 ps gate delay. IEEE international electron devices meeting, IEDM 2007; 2007. p. 651-4.
10. Weinberg Z.A. On tunnelling in metal-oxide-silicon structures. J Appl Phys 53 (1982) 5052-5056
11. Pavan P., Bez R., Olivo P., and Zanoni E. Flash memory cells - an overview. Proc IEEE 85 8 (1997) 1248-1271
12. Cappelletti P, Bez R, Cantarelli D, Fratin L. Failure mechanisms of flash cell in program/erase cycling. IEEE international electron devices meeting, IEDM 1994; 1994. p. 291-4.
13. Bez R., Camerlenghi E., Mondelli A., and Visconti A. Introduction to flash memory. Proc IEEE 91 4 (2003) 489-502
14. Yamada S, Hiura Y, Yamane T, Amemiya K, Ohshima Y, Yoshikawa K. Degradation mechanism of flash EEPROM programming after program/erase cycles. IEEE international electron devices meeting, IEDM 1993; 1993. p. 23-6.
15. Kameyama H, Okuyama Y, Kamohara S, Kubota K, Kume H, Okuyama K, et al. New data retention mechanism after endurance stress on flash memory. In: IEEE 00CH37059 38th annual international reliability physics symposium; 2000. p. 194-8.
16. Cappelleti P, Bez R, Mondelli A, Visconti A. What we have learned on flash memory reliability in the last ten years. IEEE international electron devices meeting, IEDM 2004; 2004. p. 489-92.
17. Raszka J, Advani M, Tiwari V, Varisco L, Der Hacobian N, Mittal A, et al. A embedded flash memory for security applications in a 0.13 μm CMOS logic process. In: IEEE international solid-state circuits conference; 2004 [0-7803-8267-6/04].
18. Cappelletti P., Bez R., Cantarelli D., and Ravazzi L. CAST: an electrical stress test to monitor single bit failures in flash-EEPROM structures. Microelectron Reliab 37 3 (1997) 473-481
19. 7 w/e cycles. In: IEEE 98CH36173 36th annual international reliability physics symposium; 1998. p. 378-81.
20. Shiner RE, Caywood JM, Euzent BL. Data retention in EPROMS. In: Reliability physics symposium; 1980. p. 238-43.
21. Sharma A.K. Semiconductor memories: technology, testing, and reliability (2002), Wiley-IEEE Press
22. IEEE-SA Standards Board. In: IEEE standard definitions and characterization of floating gate semiconductor arrays, IEEE Std, vol. 1005; 1998. p. 1-23.