A logic CMOS compatible Flash EEPROM for small scale integration

Proceedings of the International Conference on Microelectronics, ICM

Volumn 2003-January, Issue , 2003, Pages 348-351

  Shalchian, M ^a,b   Atarodi, S M ^a  

^a SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

^b SunSem Sdn Bhd   (Malaysia)

Author keywords

Capacitors; CMOS logic circuits; CMOS process; CMOS technology; Doping; EPROM; Fabrication; Geometry; Logic devices; Nonvolatile memory

Indexed keywords

BANDPASS FILTERS; CAPACITORS; CELLS; CMOS INTEGRATED CIRCUITS; CYTOLOGY; DATA STORAGE EQUIPMENT; DIGITAL STORAGE; DOPING (ADDITIVES); FABRICATION; GEOMETRY; LOGIC CIRCUITS; LOGIC DEVICES; MICROELECTRONICS; NONVOLATILE STORAGE; PROM; SEMICONDUCTOR STORAGE;

CMOS LOGIC CIRCUITS; CMOS PROCESSS; CMOS TECHNOLOGY; EPROM; NON-VOLATILE MEMORY;

MEMORY ARCHITECTURE;

EID: 84945276000     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICM.2003.237930     Document Type: Conference Paper

References (6)

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2. J. Van Houdt et. al.., "A 5V/3.3V-compatible Flash EEPROM cell with a 400ns/70us programming time," Proc. 5th Biennial Nonvolatile Memory Technology Review, Linthicum Heights, Md., pp. 54-57, 1993.
3. SST Technical Paper, "Super Flash EEPROM technology," 701-05 2/00, March 1999.
4. M. Shalchian, S. M. Atarodi, "The effects of removing LDD layer on the performance of a single poly flash memory cell", IEE Electronics letters, submitted for publication.
5. Paolo Cappelletti, Carla Golla, Piero Olivo, Enrico zanoni, FLASH MEMORIES, 3rd ed., Massachusetts: Kluwer Academic Press, 2001, pp. 165-176.
6. K. Yashikawa, et. al., "A Flash EEPROM cell scaling including tunnel oxide limitation," Proc. European Silid State Device Res. Conf., p. p/2, 1990