SiGe BiCMOS technology with 3.0 ps gate delay

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 651-654

  Rucker H ^a   Heinemann, B ^a   Barth, R ^a   Bauer, J ^a   Blum, K ^a   Bolze, D ^a   Drews, J ^a   Fischer, G G ^a   Fox, A ^a   Fursenko, O ^a   Grabolla, T ^a   Haak, U ^a   Hoppner W ^a   Knoll, D ^a   Kopke K ^a   Kuck, B ^a   Mai, A ^a   Marschmeyer, S ^a   Morgenstern, T ^a   Richter, H H ^a   Schley, P ^a   Schmidt, D ^a   Schulz, K ^a   Tillack, B ^a   Weidner, G ^a   Winkler, W ^a   Wolansky, D ^a   Wulf, H E ^a   Yamamototo, Y ^a   more..

^a IHP   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES; SEMICONDUCTING GERMANIUM COMPOUNDS; SEMICONDUCTING SILICON; SILICON ALLOYS; TECHNOLOGY;

EMITTER AREA; GATE DELAYS; HIGH SPEEDS; MAXIMUM OSCILLATION FREQUENCY; SIGE BICMOS TECHNOLOGY; TRANSIT FREQUENCIES;

BICMOS TECHNOLOGY;

EID: 50249113791     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4419028     Document Type: Conference Paper

References (7)

1. T=350/300 GHz and gate delay below 3.3 ps", IEDM 2004, p. 247.
2. B. Heinemann et al., "Low-parasitic collector construction for high-speed SiGe:C HBTs", IEDM 2004, p. 251.
3. J. Böck et al, "3.3 ps SiGe bipolar technology", IEDM 2004, p. 255.
4. K. Ishii et al., "3.21 ps ECL gate using InP/InGaAs DHBT technology", Electronics Lett., vol. 39, p. 1434, 2003
5. max airgap isolated 0.13 μm BiCMOS technology featuring on-chip high quality passives", BCTM 2006.
6. H. Rücker et al., "SiGe:C BiCMOS technology with 3.6 ps gate delay", IEDM 2003, p. 121.
7. T PFET, and record circuit performance for millimeter-wave digital and analog system-on- chip applications", VLSI Symposium 2007.