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Volumn , Issue , 2007, Pages 897-900

Estimation of capacitive crosstalk-induced short-circuit energy

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; CIRCUIT SIMULATION; CROSSTALK; DIGITAL CIRCUITS; ELECTRIC POWER UTILIZATION; SHORT CIRCUIT CURRENTS;

EID: 34548853172     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378070     Document Type: Conference Paper
Times cited : (1)

References (8)
  • 6
    • 84886736952 scopus 로고    scopus 로고
    • New Generation of Predictive Technology Model for sub-45nm Design Exploration
    • Online, Available
    • W. Zhao and Y. Cao, "New Generation of Predictive Technology Model for sub-45nm Design Exploration," in International Symposium on Quality Electronic Design, 2006, pp. 585-590. [Online]. Available: http://www.eas.asu.edu/~ptm.
    • (2006) International Symposium on Quality Electronic Design , pp. 585-590
    • Zhao, W.1    Cao, Y.2
  • 8
    • 0033685443 scopus 로고    scopus 로고
    • Clarinet: A Noise Analysis Tool for Deep Submicron Design
    • R. Levy et al., "Clarinet: A Noise Analysis Tool for Deep Submicron Design," in Proceedings of the Design Automation Conference, 2000, pp. 233-238.
    • (2000) Proceedings of the Design Automation Conference , pp. 233-238
    • Levy, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.