Analysis and future trend of shortcircuit power

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 9, 2000, Pages 10231030-

  Nose, Koichi ^a   Sakurai, Takayasu ^a  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

Lowpower design; Power modeling and estimation; Simulation; VLSI

Indexed keywords

EID: 33747496672     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (6)

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2. N. Hedenstierna and K. Jeppson, "CMOS circuit speed and buffer optimization," IEEE Trans. ComputerAided Design, vol. CAD6, pp. 270281, Mar. 1987
3. S. Vemuru, N. Scheinberg, and E. Smith, "Shortcircuit power dissipation formula for CMOS gates," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 2, 1993, pp. 13331335.
4. A. Hirata, H. Onodera, and K. Tamaru, "Shortcircuit power dissipation formula for static CMOS gates," in Karuizawa Proc. Workshop Circuits and Systems, July 1996, pp. 245250.
5. T. Sakurai and A.R. Newton, "Alphapower law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE J. SolidState Circuits, vol. 25, pp. 584594, Apr. 1990.
6. "Delay analysis of seriesconnected MOSFET circuits," IEEE J. SolidState Circuits, vol. 26, pp. 122131, Feb. 1991.