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Volumn 2, Issue , 1996, Pages 477-480
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High throughput 16 by 16 bit multiplier for DSP cores
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Author keywords
[No Author keywords available]
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Indexed keywords
CMOS INTEGRATED CIRCUITS;
COMPUTER SIMULATION;
DIGITAL SIGNAL PROCESSING;
INTEGRATED CIRCUIT LAYOUT;
LOGIC CIRCUITS;
LOGIC GATES;
PERFORMANCE;
PIPELINE PROCESSING SYSTEMS;
CLOCK FREQUENCY;
CLOCKING;
DIGITAL SIGNAL PROCESSING CORES;
DUAL RAIL DOMINA;
DYNAMIC LOGIC;
LATENCY CYCLES;
THROUGHPUT;
MULTIPLYING CIRCUITS;
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EID: 0029708262
PISSN: 02714310
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (6)
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References (2)
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