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Eurasip Journal on Embedded Systems

Volumn 2007, Issue , 2007, Pages

A shared memory module for asynchronous arrays of processors

(3) Meeuwsen, Michael J a Yu, Zhiyi a Baas, Bevan M a

a University of California (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 34250900349 PISSN: 16873955 EISSN: 16873963 Source Type: Journal
DOI: 10.1155/2007/86273 Document Type: Article

Times cited : (5)

References (12)

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2
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- Morgan Kaufmann San Francisco, Calif, USAMemory Hierarchy Design3rd
- J. L. Hennessy D. A. Patterson Computer Architecture, A Quantitative Approach. Morgan Kaufmann San Francisco, Calif, USA Memory Hierarchy Design 3rd 2003
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- Hennessy, J.L.¹ Patterson, D.A.²

3
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- An asynchronous array of simple processors for DSP applications
- San Francisco, Calif, USA
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- (2006) IEEE International Solid-State Circuits Conference (ISSCC '06) , pp. 428-429
- Yu, Z.¹ Meeuwsen, M.J.² Apperson, R.³

4
- 0036045884
- Scratchpad memory: A design alternative for cache on-chip memory inembedded systems
- Estes Park, Colo, USA
- R. Banakar S. Steinke B.-S. Lee M. Balakrishnan P. Marwedel Scratchpad memory: a design alternative for cache on-chip memory inembedded systems. Proceedings of the 10th International Symposium on Hardware/Software Codesign (CODES '02) Estes Park, Colo, USA 2002 73 78
- (2002) Proceedings of the 10th International Symposium on Hardware/Software Codesign (CODES '02) , pp. 73-78
- Banakar, R.¹ Steinke, S.² Lee, B.-S.³ Balakrishnan, M.⁴ Marwedel, P.⁵

5
- 23044524059
- On-chip vs. off-chip memory: The data partitioning problem in embedded processor-based systems
- P. R. Panda N. D. Dutt A. Nicolau On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. ACM Transactions on Design Automation of Electronic Systems 5 3 2000 682 704
- (2000) ACM Transactions on Design Automation of Electronic Systems , vol.5 , Issue.3 , pp. 682-704
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- A case for intelligent RAM
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- (1997) IEEE Micro , vol.17 , Issue.2 , pp. 34-44
- Patterson, D.¹ Anderson, T.² Cardwell, N.³

7
- 0033688597
- Smart memories: A modular reconfigurable architecture
- Vancouver, BC, Canada
- K. Mai T. Paaske N. Jayasena R. Ho W. J. Dally M. A. Horowitz Smart memories: a modular reconfigurable architecture. Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA '00) Vancouver, BC, Canada 2000 161 171
- (2000) Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA '00) , pp. 161-171
- Mai, K.¹ Paaske, T.² Jayasena, N.³ Ho, R.⁴ Dally, W.J.⁵ Horowitz, M.A.⁶

8
- 4143066042
- A parallel programmable energy-efficient architecture for computationally-intensive DSP systems
- Pacific Grove, Calif, USA
- B. M. Baas A parallel programmable energy-efficient architecture for computationally-intensive DSP systems. Proceedings of the 37th Asilomar Conference on Signals, Systems and Computers (ACSSC '03) Pacific Grove, Calif, USA 2 2003 2185 2192
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- Baas, B.M.¹

9
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- A full-rate software implementation of an IEEE 802.11a compliant digital baseband transmitter
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- M. J. Meeuwsen O. Sattari B. M. Baas A full-rate software implementation of an IEEE 802.11a compliant digital baseband transmitter. Proceedings of IEEE Workshop on Signal Processing Systems (SIPS '04) Austin, Tex, USA 2004 124 129
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- Meeuwsen, M.J.¹ Sattari, O.² Baas, B.M.³

10
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- Stanford University Stanford, Calif, USA
- D. M. Chapiro Globally-asynchronous locally-synchronous systems. Stanford University Stanford, Calif, USA 1994
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11
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- University of California, Davis Davis, Calif, USA
- R. W. Apperson A dual-clock FIFO for the reliable transfer of high-throughput data between unrelated clock domains. University of California, Davis Davis, Calif, USA 2004
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12
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- Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.