Copper electrodeposition for 3D integration

DTIP of MEMS and MOEMS - Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS

Volumn , Issue , 2008, Pages 127-131

  Beica, Rozalia ^a   Sharbono, Charles ^a   Ritzdorf, Tom ^a  

^a Semitool Incorporated   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; COPPER; ELECTRODEPOSITION; ELECTRONICS INDUSTRY; MEMS; MICROELECTROMECHANICAL DEVICES; OPTICAL INTERCONNECTS; PACKAGING; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICES; SILICON WAFERS; TECHNOLOGY; THREE DIMENSIONAL;

3-D INTEGRATIONS; 3-D PACKAGING; ADVANCED PACKAGING; ADVANCED TECHNOLOGIES; CHIP INTEGRATIONS; COMPACT PACKAGES; COPPER DAMASCENE INTERCONNECTS; COPPER ELECTRODEPOSITIONS; ELECTRONIC DEVICES; ELECTRONIC PRODUCTS; FILL PROCESS; GENERAL TRENDS; NEW TECHNOLOGIES; PROCESS OPTIMIZATIONS; SEMICONDUCTOR INDUSTRIES; THREE-DIMENSIONAL (3D); THROUGH-SILICON-VIA; VERTICAL INTEGRATIONS; VOID-FREE;

INTEGRATION;

EID: 62249169291     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DTIP.2008.4752967     Document Type: Conference Paper

References (17)

1. S. Lassig, "Manufacturing Integration Consideration of Through-Silicon Via Etching", Solid State Technology, December, 2007
2. D.M. Jang, C. Ryu, K,Y.Lee, B.H.Cho, J. Kim, T.S.Oh, W.J. Lee, and J. Yu, "Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)", Electronic Components and Technology Conference Proceedings, pp. 847, 2007
3. Yole Development, "3D IC&TSV Report", Report #YD4285, Electronics Industry Market Research and Knowledge Network, http://www.electronics.ca/reports/microelectronics/3d-ic-tsv.html, November 2007
4. D. Schmauch, B. Kim, and T. Ritzdorf, "3D Packaging Enabled with Electrochemical Deposition Techniques from Varied Electronic Industry Segments," Pan Pacific Microelectronics Symposium, January 2006.
5. B. Kim, "EMC-3D Consortium Targets Cost-Effective TSV Interconnects", Semiconductor International, February 1, 2007
6. "IBM tips TSV 3D chip stacking technique", Solid State Technology,
7. D. Schmauch, J.M. Thevenoud, R. Beica, M. Wimplinger, "3D Packaging - How to Build 3D Packages from Design through Materials & Equipment", Advanced Packaging, February 2008
8. D. Edelstein, et al., Technical Digest, IEEE International Electron Devices Meeting, pp. 773, 1997
9. S. Venkatesan, et al., Technical Digest, IEEE International Electron Devices Meeting, pp. 769, 1997
10. B. Kim, and T. Ritzdorf, "High Aspect Ratio Via Filling with Copper for 3D Integration", Semiconductor Equipment and Materials International, Korea, 2006
11. F. Niklaus, J.Q. Lu, J.J. McMahon, J. Hu, S.H. Lee, T.S. Cale, R.J. Gutmann, "Wafer Level 3D Integration Technology Platform for ICs and MEMS", http://www.ee.kth.se/php/modules/publications/reports/2005/IR-EE-MST 2005 001.pdf. 2005
12. J. Vardaman, "3-D Through-Silicon Vias Become a Reality", Semiconductor International, http://www.semiconductor.net/article/ CA6445435.html?nid=3572, June 2007
13. U. Landau, "Copper Metallization of Semiconductor Interconnects-issues and prospects", CMP Symposium, Abstract #505, Electrochemical Society Meeting, pp.22-27, 2000
14. B. Black, "3D A Revolution in Design", http://www.cc.gatech. edu/∼loh/3D-tutorial/3D-black.pdf
15. P.H. Haumesser, et al., "ECD Seed Copper Layer for Seed Ehancement in Advanced Interconnects", 203rd Meeting of the Electrochemical Society, 2003
16. L.Chen, and T.Ritzdorf, "ECD Seed Layer for inlaid copper metallization", 195th ECS meeting, Symposium G1, Proceedings of the ULSI Fabrication and semiconductor/metal deposition II, Seattle, WA, May 2-6, 1999
17. M. Schlesinger, M. Paunovic, Modern Electroplating, Fourth Edition, John Wiley & Sons, Inc., pp.61-81, 2000