3-D Through-silicon vias become a reality

Semiconductor International

Volumn 30, Issue 6, 2007, Pages 36-40

  Vardaman, Jan ^a,b,c,d  

^a TECHSEARCH INTERNATIONAL   (United States)

^b IEEE

^c IEEE ^*

^d Fabless Semiconductor Association

Author keywords

[No Author keywords available]

Indexed keywords

EID: 34250790620     PISSN: 01633767     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (5)

1. B. Kim. "EMC-3D Consortium Targets Cost-Effective TSV Interconnects," Semiconductor International, 2007, Vol. 30, No. 2, p. SP-7.
2. P. Garrou and E.J. Vardaman, "3D Integration at the Wafer Level," TechSearch International Inc., March 2006.
3. T. Fukushima, Y. Yamada, H. Kikuchi, T. Tanaka, and M. K. Oyanagi, "Ultimate Super Chip Integration," International Conf. on Electronic Packaging (ICEP), April 2006.
4. M. Ooishi, "Vertical Stacking to Redefine Chip Design," Nikkei Electronics Asia, April 2007, p. 20.
5. P Garrou, "Posturing & Positioning in 3-D ICs," Semiconductor International. 2007, Vol. 30, No. 4, p. 88.