Reliability evaluation for flip-chip electronic packages under high temperature and moisture condition using moire

10th Electronics Packaging Technology Conference, EPTC 2008

Volumn , Issue , 2008, Pages 633-638

  Park, Jin Hyoung ^a   Jang, Kyung Woon ^a   Paik, Kyung Wook ^a   Lee, Soon Bok ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; DELAMINATION; ELECTRONICS PACKAGING; FRACTURE TOUGHNESS; GLASS; INTEGRATED CIRCUIT INTERCONNECTS; INTERFEROMETRY; MOIRE FRINGES; MOISTURE; PHASE SHIFT; SHEAR STRAIN; SUBSTRATES; SWELLING;

ANISOTROPICALLY CONDUCTIVE FILMS; COEFFICIENT OF MOISTURE EXPANSION; ENVIRONMENTAL COMPATIBILITY; FLIP CHIP INTERCONNECTS; INTERFACIAL DELAMINATION; INTERFACIAL FRACTURE TOUGHNESS; PHASE SHIFTING METHODS; RELIABILITY PERFORMANCE;

FLIP CHIP DEVICES;

EID: 63049091035     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2008.4763504     Document Type: Conference Paper

References (20)

1. A.M. Lyons et al., "A New Approach to Using Anisotropically Conductive Adhesives for Flip-Chip Assembly," IEEE Trans, on Comp. Pack. & Manuf. Tech. - Part A, Vol. 19 (1996), pp. 5-11.
2. IS. Rasul, "Chip on paper technology utilizing anisotropically conductive adhesive for smart label applications," Microelec. Reliab., Vol. 44 (2004), pp. 135-140.
3. Han B. and Kunthong P., "Micro-Mechanical Deformation Analysis of Surface Laminar Circuit in Organic Flip-Chip Package: An Experimental Study," Journal of electronic packaging, Vol. 122 No. 4 (2000), pp. 294-300.
4. Xie, H., Boay, C.G., Asundi, A., Jin, Y., Lu, Y., Ngoi, B.K.A., Zhong, Z., Thermal deformation measurement of electronic package using advanced moire methods , Proceedings of the Electronic Packaging Technology Conference, EPTC, 2000-January, 2000, 163-168
5. Miller, M.R., Mohammed, I., and Ho, P.S., "Quantitative strain analysis of flip-chip electronic packages using phase-shifting moire interferometry," Optics and lasers in engineering, Vol. 36 No. 2 (2001), pp. 127-139.
6. Wang, Guotao, Zhao, Jie-Hua, Ding, Min, and Ho, P.S., "Thermal deformation analysis on flip-chip packages using high resolution moire interferometry," 2002 ITHERM (2002 Thermal and Thermomechanical Phenomena in Electronic Systems, The Eighth Intersociety Conference), 2002, pp. 869-875.
7. D. Post, B. Han, P. Ifju, High Sensitivity Moire. Springer-Verlag (New York, 1994), pp. 118.
8. A.F. Bastawros, A.S. Voloshin, P. Rodogoveski, "Determination of Thermally Induced Deformations in Electronic Packages by Moiré Interferometry," In Proceeding of 39th Electronic Components & Technology Conference (ECTC '89), 1989, pp. 864-868.
9. B. Han and Y. Guo, "Determination of an Effective Coefficient of Thermal Expansion of Electronic Packaging Components: A Whole-Field Approach," IEEE Components, Packaging, and Manufacturing Technology-Part A, Vol. 19, No. 2 (1996), pp. 240-247.
10. S. Liu, et al., "Study of Delaminated Plastic Packages by High Temperature Moire and Finite Element Method," IEEE Trans. on Components, Packaging, and Manufacturing Technology - Part A, Vol. 20, No. 4 (1997), pp505-512.
11. Y. Guo and S. Liu, "Development in Optical Methods for Reliability Analysis in Electronic Packaging Applications," ASME Journal of Electronic Packaging, Vol. 120 (1998), pp. 186-193.
12. B. Han, Y. Guo, C.K. Lim, D. Caletka, "Verification of Numerical Models Used in Microelectronics Packaging Design by Interferometric Displacement Measurement Methods," ASME Journal of Electronic Packaging, Vol. 118 (1996), pp. 157-163.
13. W.D. Driel, G.Q. Zhang, J.H.J. Janssen, LJ. Ernst, F. Su, K.S. Chian, et al., "Prediction and verification of process induced warpage of electronic packages," Microelectronics Reliability, Vol. 43 (2003), pp. 765-774.
14. K. Verma, S.B. Park, B. Han, "On the Design Parameters of Flip-Chip PBGA Package Assembly for Optimum Solder Ball Reliability," IEEE Trans, on Components and Packaging Technology, Vol. 24, No. 2 (2001), pp. 300-307.
15. W. Zhang, D. Wu, et al., "The Effect of Underfill Epoxy on Warpage in Flip-Chip Assmeblies," IEEE Trans, on Components, Packaging, and Manufacturing Technology-Part A, Vol. 21, No. 2 (1998), pp. 323-329.
16. Yang, Se Young and Lee, Soon-Bok, "Developing phase-shifting micro mow interferometry using phase shifter with rough resolution and by shifting specimen grating," 2001 EMAP (2001 Electronic Materials and Packaging), Jeju, Korea, Nov. 2001, pp. 399-403.
17. Seungbae, P., "Predictive Model for Optimized Design Parameters in Flip-Chip Packages and Assemblies," IEEE Trans, on Components and Packaging Technology, Vol. 30, No. 2 (2007), pp. 294-301.
18. Lei L. Mercado, "Failure Mechanism Study of Anisotropic Conductive Film (ACF) Packages," IEEE Trans, on Components and Packaging Technology, Vol. 26, No. 3 (2003), pp. 509-516.
19. X. Q. Shi, "Effect of Hygrothermal Aging on Interfacial Reliability of Silicon/Underfill/FR-4 Assembly," IEEE Trans, on Components and Packaging Technology, Vol. 31, No. 0 (2008), pp. 94-103.
20. X. Q. Shi, "Determination of Fracture Toughness of Underfill/Chip Interface With Digital Image Speckle Correlation Technique," IEEE Trans, on Components and Packaging Technology, Vol. 30, No. 1 (2007), pp. 101-109.