Designing high-speed adders in power-constrained environments

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 56, Issue 2, 2009, Pages 172-176

  Frustaci, Fabio ^a   Lanuzza, Marco ^a   Zicari, Paolo ^a   Perri, Stefania ^a   Corsonello, Pasquale ^a  

^a UNIVERSITY OF CALABRIA   (Italy)

Author keywords

Clock precharged dynamic logic; Data driven dynamic logic (D3L); Data precharged dynamic logic; Parallel prefix adder

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; METALS; MOS DEVICES; OXIDE SEMICONDUCTORS;

COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TECHNOLOGIES; DYNAMIC LOGIC; ENERGY DELAY PRODUCT; HIGH-SPEED ADDERS; KOGGE-STONE ADDER; NOVEL TECHNIQUES; PARALLEL PREFIX ADDER; SPEED PERFORMANCE;

COMPUTER CIRCUITS;

EID: 62749102527     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2008.2010187     Document Type: Article

References (14)

1. R. Shalem, E. John, and L. K. John, "A novel low power energy recovery full adder cell," in Proc. 9th Great Lakes Symp. VLSI, Ypsilanti, MI, Mar. 4-6, 1999, pp. 380-383.
2. S. Mathew, M. Anders, R. K. Krishnamurthy, and S. Borkar, "A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core," IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 689-695, May 2003.
3. J. Kim, K. Lee, and H.-J. Yoo, "A 372 ps 64-bit adder using fast pull-up logic in 0.18-μm CMOS," in Proc. IEEE ISCAS, Island of KOS, Greece, May 21-24, 2006, pp. 13-16.
4. S. Kao, R. Zlatanovici, and B. Nikolic, "A 240 ps 64 b carry-lookahead adder in 90 nm CMOS," in Proc. IEEE Int. Solid-State Circuits Conf. San Francisco, CA, Feb. 6-9, 2006, pp. 1735-1744.
5. R. Zlatanovici and B. Nikolic, "Power-performance optimization for custom digital circuits," in Proc. PATMOS, Leuven, Belgium, Sep. 2005, pp. 404-414.
6. D. Patil, O. Azizi, M. Horowitz, R. Ho, and R. Ananthraman, "Robust energy-efficient adder topologies," in Proc. 18th IEEE Symp. Comput. Arith. ARITH, Montpellier, France, Jun. 25-27, 2007, pp. 16-28.
7. V. G. Oklobdzija, B. R. Zeydel, H. Q. Dao, S. Mathew, and R. Krishnamurthy, "Comparison of high-performance VLSI adders in the energy-delay space," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 754-758, Jun. 2005.
8. H. Kawaguchi and T. Sakurai, "A reduced clock-swing flip-flop (RCSFF) for 63% power reduction," IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 807-811, May 1998.
9. 3L)," in Proc. IEEE ISCAS, Geneva, Switzerland, 2000, pp. 752-755.
10. J. R. Yuan, C. Svensson, and P. Larsson, "New domino logic precharged by clock and data," Electron. Lett., vol. 29, no. 25, pp. 2188-2189, Dec. 9, 1993.
11. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 2002.
12. P. M. Kogge and H. S. Stone, "A parallel algorithm for the efficient solution of a general class of recurrence equations," IEEE Trans. Comput., vol. C-22, no. 8, pp. 786-793, Aug. 1973.
13. A. Solomatnikov, D. Somasekhar, K. Roy, and C.-K. Koh, "Skewed CMOS: Noise-immune high-performance low-power static circuit family," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 4, pp. 469-476, Aug. 2002.
14. I. Sutherland, R. Sproull, and D. Harris, Logical Effort. San Francisco, CA: Morgan Kaufmann, 1999.