Comparison of high-performance VLSI adders in the energy-delay space

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 6, 2005, Pages 754-758

  Oklobdzija, Vojin G ^a   Zeydel, Bart R ^a   Dao, Hoang Q ^a   Mathew, Sanu ^b   Krishnamurthy, Ram ^b  

^a Davis   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Adders; Digital arithmetic; Digital circuits; Energy delay optimization

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; DIGITAL ARITHMETIC; DIGITAL CIRCUITS; LOGIC GATES; OPTIMIZATION; VLSI CIRCUITS;

CRITICAL-PATH DELAY ESTIMATION; ENERGY-DELAY OPTIMIZATION; LOAD EFFECTS; LOGICAL EFFORTS (LE);

ADDERS;

EID: 23744434768     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.848819     Document Type: Review

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