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Volumn , Issue , 2008, Pages 227-233

Dynamic test scheduling for analog circuits for improved test quality

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC TESTS; LNA CIRCUITS; SET COVER METHODS; SPECIFICATION PARAMETERS; TEST QUALITIES; TEST SCHEDULING; TEST TIME; TEST TIME REDUCTIONS;

EID: 62349138241     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2008.4751866     Document Type: Conference Paper
Times cited : (11)

References (12)
  • 2
    • 62349140804 scopus 로고    scopus 로고
    • Automatic test generation of linear analog circuits under parameter variations
    • C.-J. R. Shi and M. Tian, "Automatic test generation of linear analog circuits under parameter variations," IEEE/ACM Design Automation Conference, 1998.
    • (1998) IEEE/ACM Design Automation Conference
    • Shi, C.-J.R.1    Tian, M.2
  • 3
    • 84886481952 scopus 로고    scopus 로고
    • Low-cost alternate EVM test for wireless receiver systems
    • A. Haider and A. Chatterjee, "Low-cost alternate EVM test for wireless receiver systems," IEEE VLSI Test Symposium, pp. 255-260, 2005.
    • (2005) IEEE VLSI Test Symposium , pp. 255-260
    • Haider, A.1    Chatterjee, A.2
  • 5
    • 0033733147 scopus 로고    scopus 로고
    • Test generation for accurate prediction of analog specifications
    • R. Voorakaranam and A. Chatterjee, "Test generation for accurate prediction of analog specifications," IEEE VLSI Test Symposium, pp. 137-142, 2000.
    • (2000) IEEE VLSI Test Symposium , pp. 137-142
    • Voorakaranam, R.1    Chatterjee, A.2
  • 7
    • 34548741833 scopus 로고    scopus 로고
    • Variance reduction for supply ramp based cheap RF test alternatives
    • S. Krishnan, R. Jonker, and L. v. d. Logt, "Variance reduction for supply ramp based cheap RF test alternatives," IEEE European Test Symposium, pp. 55-62, 2007.
    • (2007) IEEE European Test Symposium , pp. 55-62
    • Krishnan, S.1    Jonker, R.2    Logt, L.V.D.3
  • 9
    • 0026175294 scopus 로고
    • Optimal ordering of analog integrated circuit tests to minimize test time
    • S. Huss and R. Gyurcsik, "Optimal ordering of analog integrated circuit tests to minimize test time," in IEEE/ACM Design Automation Conference, 1991, pp. 494-499.
    • (1991) IEEE/ACM Design Automation Conference , pp. 494-499
    • Huss, S.1    Gyurcsik, R.2
  • 11
    • 0032661188 scopus 로고    scopus 로고
    • Test metrics for analog parametric faults
    • S. Sunter and N. Nagi, "Test metrics for analog parametric faults," IEEE VLSI Test Symposium, pp. 226-234, 1999.
    • (1999) IEEE VLSI Test Symposium , pp. 226-234
    • Sunter, S.1    Nagi, N.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.