Test generation for accurate prediction of analog specifications

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2000, Pages 137-142

  Voorakaranam, Ram ^a   Chatterjee, Abhijit ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; SPECIFICATIONS;

ANALOG CIRCUITS; CIRCUIT SPECIFICATIONS; CIRCUIT UNDER TEST; LINEAR MODELS; TEST GENERATION; TEST STIMULUS;

VLSI CIRCUITS;

EID: 0033733147     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (15)