Maze routing with buffer insertion and wiresizing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 10, 2002, Pages 1205-1208

  Lai, Minghorng ^a   Wong, D F ^b  

^a CADENCE DESIGN SYSTEMS   (United States)

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

Buffer insertion; Routing; Wiresizing

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; DYNAMIC PROGRAMMING; GRAPH THEORY; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; TABLE LOOKUP;

BUFFER INSERTION; ELMORE DELAY; MAZE ROUTING; WIRESIZING;

VLSI CIRCUITS;

EID: 0036811340     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.802260     Document Type: Article

References (10)

1. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990.
2. "International technology roadmap for semiconductors," Semiconductor Industry Association, San Jose, CA, Nov. 2001.
3. H. Zhou, D. F. Wong, I.-M. Liu, and A. Aziz, "Simultaneous routing and buffer insertion with restrictions on buffer locations," in Proc. ACM/IEEE Design Automation Conf., 1999, pp. 96-99.
4. W. C. Elmore, "The transient response of damped linear network with particular regard to wideband amplifiers," J. Applied Phys., vol. 19, pp. 55-63, Jan. 1948.
5. R. Gupta, B. Krauter, B. Tutuianu, J. Willis, and L. T. Pileggi, "The Elmore delay as bound for RC trees with generalized input signals," in Proc. ACM/IEEE Design Automation Conf., 1995, pp. 364-369.
6. C. J. Alpert, G. Gandham, J. Hu, J. L. Neves, S. T. Quay, and S. S. Sapatnekar, "Steiner tree optimization for buffers, blockages, and bays," IEEE Trans. Computer-Aided Design, vol. 20, pp. 556-562, Apr. 2001.
7. J. Cong, J. Fang, and K.-Y. Khoo, "Implicit connection graph maze routing algorithm for ECO routing," in Proc. Int. Conf. Computer-Aided Design, 1999, pp. 163-167.
8. J. Lillis, C.-K. Cheng, and T.-T. Y. Lin, "Optimal and efficient buffer insertion and wire sizing," in Proc. IEEE Custom Integrated Circuits Conf., 1995, pp. 259-262.
9. ____, "Optimal wire sizing and buffer insertion for low power and a generalized delay model," in Proc. Int. Conf. Computer-Aided Design, 1995, pp. 138-143.
10. L. P. P. P. van Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay," in Proc. IEEE Int. Symp. Circuits Syst., vol. 2, 1990, pp. 865-868.