Voltage Island aware floorplanning for power and timing optimization

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2006, Pages 389-394

  Lee, Wan Ping ^a   Liu, Hung Yi ^a   Chang, Yao Wen ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; DYNAMIC PROGRAMMING; ELECTRIC POWER UTILIZATION; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUITS; MATHEMATICAL PROGRAMMING; OPTIMIZATION; SYSTEMS ENGINEERING; TIME MEASUREMENT; TIMING CIRCUITS;

CHIP DESIGNS; COMPUTER-AIDED DESIGN; EFFECTIVE VOLTAGE; EXPERIMENTAL RESULTS; FLOOR-PLANNING; FLOORPLANNER; INTERNATIONAL CONFERENCES; LEVEL SHIFTERS; MULTIPLE SUPPLY VOLTAGES; NET LIST; OPTIMAL SOLUTIONS; POWER CONSUMPTION (CE); POWER CONSUMPTION REDUCTION; POWER SAVINGS; TIMING CONSTRAINTS; TIMING OPTIMIZATION; VOLTAGE ASSIGNMENTS; VOLTAGE DOMAINS; VOLTAGE ISLANDS;

ENERGY CONSERVATION;

EID: 43349099463     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320063     Document Type: Conference Paper

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