SET emulation under a quantized delay model

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 25, Issue 1 SPEC. ISS., 2009, Pages 107-116

  García Valderas, Mario ^a   Entrena, Luis ^a   Fernández Cardenal, Raúl ^a   López Ongil, Celia ^a   Portela García, Marta ^a  

^a UNIVERSIDAD CARLOS III DE MADRID   (Spain)

Author keywords

Fault emulation; Fault injection; Fault tolerance; Single event transients

Indexed keywords

FAULT TOLERANCE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); TRANSIENTS;

DELAY MODELS; DIGITAL SIMULATIONS; FAULT ANALYSIS; FAULT EMULATION; FAULT INJECTION; GATE LEVEL SIMULATIONS; GATE LEVELS; SINGLE EVENT TRANSIENTS; THREE ORDERS OF MAGNITUDES;

QUALITY ASSURANCE;

EID: 62249146160     PISSN: 09238174     EISSN: 15730727     Source Type: Journal    
DOI: 10.1007/s10836-008-5081-3     Document Type: Article

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