SCOPUS 정보 검색 플랫폼

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 229-236

An industrial environment for high-level fault-tolerant structures insertion and validation

(7) Berrojo, L a Corno, F b Entrena, L c Gonzalez I a Lopez, C c Sonza Reorda, M b Squillero, G b

a PTM (Spain)

b POLITECNICO DI TORINO (Italy)

c UNIVERSIDAD CARLOS III DE MADRID (Spain)

Author keywords

Aerospace electronics; Automotive engineering; Circuit faults; Circuit testing; Design engineering; Fault tolerance; Hardware design languages; Process design; Safety; Very large scale integration

Indexed keywords

ACCIDENT PREVENTION; AUTOMOTIVE ENGINEERING; DESIGN; FAULT TOLERANCE; INTEGRATION TESTING; PROCESS DESIGN; SAFETY ENGINEERING; SAFETY TESTING;

AEROSPACE ELECTRONICS; CIRCUIT FAULTS; CIRCUIT TESTING; DESIGN ENGINEERING; HARDWARE DESIGN LANGUAGE;

VLSI CIRCUITS;

EID: 84948404797 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/VTS.2002.1011143 Document Type: Conference Paper

Times cited : (24)

References (7)

1
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- Fault Tolerant VHDL architectures for Space Applications
- Toledo (Spain)
- F. Alcala, L. Berrojo, F. Ortega, "Fault Tolerant VHDL architectures for Space Applications", Proceedings of the VHDL User's Forum, Toledo (Spain), 1997
- (1997) Proceedings of the VHDL User's Forum
- Alcala, F.¹ Berrojo, L.² Ortega, F.³

2
- 0031123369
- Fault Injection Techniques and Tools
- April
- M.C. Hsueh, T. K. Tsai, R. K. Iyer, "Fault Injection Techniques and Tools", Computer, April 1997, pp. 75-82.
- (1997) Computer , pp. 75-82
- Hsueh, M.C.¹ Tsai, T.K.² Iyer, R.K.³

3
- 0030402886
- A Fault Injection Technique for VHDL Behavioral-Level Models
- Winter
- T.A. Delong, B.W. Johnson, J.A. Profeta III, "A Fault Injection Technique for VHDL Behavioral-Level Models", IEEE Design & Test of Computers, Winter 1996, pp. 24-33
- (1996) IEEE Design & Test of Computers , pp. 24-33
- Delong, T.A.¹ Johnson, B.W.² Profeta, J.A.³

4
- 0002475610
- New Techniques for Accelerating Fault Injection in VHDL descriptions
- July
- B. Parrotta, M. Rebaudengo, M. Sonza Reorda, M. Violante, "New Techniques for Accelerating Fault Injection in VHDL descriptions", IEEE International On-Line Test Workshop 2000, July 2000, pp. 61-66
- (2000) IEEE International On-Line Test Workshop 2000 , pp. 61-66
- Parrotta, B.¹ Rebaudengo, M.² Sonza Reorda, M.³ Violante, M.⁴

5
- 0034450666
- Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection
- R. Velazco, S. Rezgui, R. Ecoffet, "Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection", IEEE Transactions on Nuclear Science, Vol. 47, No. 6, 2000, pp. 2405-2411
- (2000) IEEE Transactions on Nuclear Science , vol.47 , Issue.6 , pp. 2405-2411
- Velazco, R.¹ Rezgui, S.² Ecoffet, R.³

6
- 28344447641
- Automatic Insertion of Fault-Tolerant Structures at the RT Level
- July
- L. Entrena, C. López, E. Olías, "Automatic Insertion of Fault-Tolerant Structures at the RT Level", IEEE International On-Line Test Workshop 2001, July 2001, pp. 48-50
- (2001) IEEE International On-Line Test Workshop 2001 , pp. 48-50
- Entrena, L.¹ López, C.² Olías, E.³

7
- 84893748923
- New Techniques for Speeding-up Fault-injection Campaigns
- submitted
- L. Berrojo, F. Corno, L. Entrena, I. González, C. Lopez, M. Sonza Reorda, G. Squillero, "New Techniques for Speeding-up Fault-injection Campaigns", submitted to DATE2002: Design Automation and Test in Europe, 2002
- DATE2002: Design Automation and Test in Europe, 2002
- Berrojo, L.¹ Corno, F.² Entrena, L.³ González, I.⁴ Lopez, C.⁵ Sonza Reorda, M.⁶ Squillero, G.⁷

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