-
1
-
-
33847761180
-
-
International Technology Roadmap for Semiconductors, 2001 Edition.
-
International Technology Roadmap for Semiconductors, 2001 Edition.
-
-
-
-
2
-
-
0034450666
-
Predicting error rate for microprocessor-based digital architectures through C.E.U. (code emulating upsets) injection
-
Dec
-
R. Velazco, S. Rezgui, and R. Ecoffet, "Predicting error rate for microprocessor-based digital architectures through C.E.U. (code emulating upsets) injection," IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2405-2411, Dec. 2000.
-
(2000)
IEEE Trans. Nucl. Sci
, vol.47
, Issue.6
, pp. 2405-2411
-
-
Velazco, R.1
Rezgui, S.2
Ecoffet, R.3
-
3
-
-
0002598384
-
Application of three physical fault injection techniques to the experimental assessment of the MARS architecture
-
Urbana/Champaign, IL, Sep
-
J. Karlsson, P. Folkesson, J. Arlat, Y. Crouzet, G. Leber, and J. Reisinger, "Application of three physical fault injection techniques to the experimental assessment of the MARS architecture," in Proc. Int. Working Conf. Dependable Computing for Critical Applications, Urbana/Champaign, IL, Sep 1995, pp. 150-161.
-
(1995)
Proc. Int. Working Conf. Dependable Computing for Critical Applications
, pp. 150-161
-
-
Karlsson, J.1
Folkesson, P.2
Arlat, J.3
Crouzet, Y.4
Leber, G.5
Reisinger, J.6
-
4
-
-
0026880102
-
Heavy ion test results for the 68020 microprocessor and the 68882 coprocessor
-
Jun
-
R. Velazco, S. Karoui, T. Chapuis, D. Benezech, and L. H. Rosier, "Heavy ion test results for the 68020 microprocessor and the 68882 coprocessor," IEEE Trans. Nucl. Sci., vol. 39, no. 3, pp. 436-440, Jun. 1992.
-
(1992)
IEEE Trans. Nucl. Sci
, vol.39
, Issue.3
, pp. 436-440
-
-
Velazco, R.1
Karoui, S.2
Chapuis, T.3
Benezech, D.4
Rosier, L.H.5
-
5
-
-
0030372099
-
SEU-hardened storage cell validation using a pulsed laser
-
Dec
-
R. Velazco, T. Calin, M. Nicolaidis, S. C. Moss, S. D. LaLumondiere, V. T. Tran, and R. Koga, "SEU-hardened storage cell validation using a pulsed laser," IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2843-2848, Dec. 1996.
-
(1996)
IEEE Trans. Nucl. Sci
, vol.43
, Issue.6
, pp. 2843-2848
-
-
Velazco, R.1
Calin, T.2
Nicolaidis, M.3
Moss, S.C.4
LaLumondiere, S.D.5
Tran, V.T.6
Koga, R.7
-
6
-
-
33745495021
-
On the proposition of an EMI-based fault injection approach
-
Jul
-
F. Vargas, D. L. Cavalcante, E. Gatti, D. Prestes, and D. Lupi, "On the proposition of an EMI-based fault injection approach," in Proc. 11th IEEE Int. On-Line Testing Symp., Jul. 2005, pp. 207-208.
-
(2005)
Proc. 11th IEEE Int. On-Line Testing Symp
, pp. 207-208
-
-
Vargas, F.1
Cavalcante, D.L.2
Gatti, E.3
Prestes, D.4
Lupi, D.5
-
7
-
-
0028018774
-
Fault injection into VHDL models: The MEFISTO tool
-
E. Jenn, J. Arlat, M. Rimen, J. Ohlsson, and J. Karlsson, "Fault injection into VHDL models: the MEFISTO tool," in Proc. FTCS-24, Int. Symp. Fault Tolerant Computing, 1994, pp. 66-75.
-
(1994)
Proc. FTCS-24, Int. Symp. Fault Tolerant Computing
, pp. 66-75
-
-
Jenn, E.1
Arlat, J.2
Rimen, M.3
Ohlsson, J.4
Karlsson, J.5
-
8
-
-
0030402886
-
A fault injection technique for VHDL behavioral-kevel models
-
Winter
-
T. A. Delong, B. W. Johnson, and J. A. Profeta, III, "A fault injection technique for VHDL behavioral-kevel models," IEEE Des. Test Comput., pp. 24-33, Winter, 1996.
-
(1996)
IEEE Des. Test Comput
, pp. 24-33
-
-
Delong, T.A.1
Johnson, B.W.2
Profeta III, J.A.3
-
9
-
-
84942514785
-
VERIFY: Evaluation of reliability using VHDL-models with embedded fault descriptions
-
Jun
-
V. Sieh, O. Tschäche, and F. Balbach, "VERIFY: evaluation of reliability using VHDL-models with embedded fault descriptions," in Proc. 27th Int. Symp. Fault Tolerant Computing, Jun. 1997, pp. 32-36.
-
(1997)
Proc. 27th Int. Symp. Fault Tolerant Computing
, pp. 32-36
-
-
Sieh, V.1
Tschäche, O.2
Balbach, F.3
-
10
-
-
84948404797
-
An industrial environment for high-level fault-tolerant structures insertion and validation
-
Monterey, CA, May
-
L. Berrojo, F. Corno, L. Entrena, I. González, C. Löpez, M. Sonza, and G. Squillero, "An industrial environment for high-level fault-tolerant structures insertion and validation," in IEEE VLSI Test Symp., Monterey, CA, May 2002, pp. 229-236.
-
(2002)
IEEE VLSI Test Symp
, pp. 229-236
-
-
Berrojo, L.1
Corno, F.2
Entrena, L.3
González, I.4
Löpez, C.5
Sonza, M.6
Squillero, G.7
-
11
-
-
0036992533
-
On the use of VHDL simulation and emulation to derive error rates
-
Grenoble, France, Sep
-
F. Lima, S. Rezgui, L. Carro, R. Velazco, and R. Reis, "On the use of VHDL simulation and emulation to derive error rates," in Proc. 6th Conf. Radiation and its Effects on Components and Systems (RADECS'01), Grenoble, France, Sep. 2001.
-
(2001)
Proc. 6th Conf. Radiation and its Effects on Components and Systems (RADECS'01)
-
-
Lima, F.1
Rezgui, S.2
Carro, L.3
Velazco, R.4
Reis, R.5
-
12
-
-
84948993581
-
Using run-time reconfiguration for fault injection in HW prototypes
-
L. Antoni, R. Leveugle, and B. Feher, "Using run-time reconfiguration for fault injection in HW prototypes," in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, 2002, pp. 245-253.
-
(2002)
Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems
, pp. 245-253
-
-
Antoni, L.1
Leveugle, R.2
Feher, B.3
-
13
-
-
33847749464
-
FPGA-based fault injection techniques for fast evaluation of fault tolerante in VLSI circuits
-
Belfast, Northern Ireland, Aug
-
P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, and M. Violante, "FPGA-based fault injection techniques for fast evaluation of fault tolerante in VLSI circuits," in Proc. Forum on Programmable Logic (FPL), Belfast, Northern Ireland, Aug. 2001.
-
(2001)
Proc. Forum on Programmable Logic (FPL)
-
-
Civera, P.1
Macchiarulo, L.2
Rebaudengo, M.3
Sonza Reorda, M.4
Violante, M.5
-
14
-
-
0035722241
-
Exploiting circuit emulation for fast hardness evaluation
-
Dec
-
_, "Exploiting circuit emulation for fast hardness evaluation," IEEE Trans. Nucl. Sci., vol. 48, no. 6, pp. 2210-2216, Dec. 2001.
-
(2001)
IEEE Trans. Nucl. Sci
, vol.48
, Issue.6
, pp. 2210-2216
-
-
Civera, P.1
Macchiarulo, L.2
Rebaudengo, M.3
Sonza Reorda, M.4
Violante, M.5
-
15
-
-
33847741140
-
Fast observation architecture for FPGA-based SEU analysis
-
Talinn, Estonia, May
-
A. Ejlali, B. M. Al-Hashimi, and S. Ghassem Miremadi, "Fast observation architecture for FPGA-based SEU analysis," in Proc. 10th European Test Symp. (ETS'05), Talinn, Estonia, May 2005.
-
(2005)
Proc. 10th European Test Symp. (ETS'05)
-
-
Ejlali, A.1
Al-Hashimi, B.M.2
Ghassem Miremadi, S.3
-
16
-
-
84860207500
-
Supporting fault tolerance in an industrial environment: The AMATISTA approach
-
I. González and L. Berrojo, "Supporting fault tolerance in an industrial environment: the AMATISTA approach," in Proc. IEEE Int. On-Line Test Workshop, 2001, pp. 178-183.
-
(2001)
Proc. IEEE Int. On-Line Test Workshop
, pp. 178-183
-
-
González, I.1
Berrojo, L.2
-
17
-
-
33745496339
-
Autonomous transient fault emulation on FPGAs for accelerating fault grading
-
Saint-Raphael, France, Jul
-
C. López-Ongil, M. García-Valderas, M. Portela- García, and L. Entrena-Arrontes, "Autonomous transient fault emulation on FPGAs for accelerating fault grading," in Int. On-Line Testing Symp., Saint-Raphael, France, Jul. 2005, pp. 43-48.
-
(2005)
Int. On-Line Testing Symp
, pp. 43-48
-
-
López-Ongil, C.1
García-Valderas, M.2
Portela- García, M.3
Entrena-Arrontes, L.4
-
18
-
-
33847739440
-
A FPGA based hardware emulator for the insertion and analysis of single event upsets in VLSI designs
-
Madrid, Spain, Sep
-
M. Aguirre, J. N. Tombs, F. Muñoz, V. Baena, A. Torralba, A. Fernández-León, F. Tortosa, and D. González- Gutiérrez, "A FPGA based hardware emulator for the insertion and analysis of single event upsets in VLSI designs," in Proc. Radiation Effects on Components and Systems Conf. (RADECS), Madrid, Spain, Sep. 2004.
-
(2004)
Proc. Radiation Effects on Components and Systems Conf. (RADECS)
-
-
Aguirre, M.1
Tombs, J.N.2
Muñoz, F.3
Baena, V.4
Torralba, A.5
Fernández-León, A.6
Tortosa, F.7
González- Gutiérrez, D.8
-
19
-
-
33847720396
-
-
Celoxica RC1000 Hardware Reference Manual, ver. 2.3, 2004.
-
"Celoxica RC1000 Hardware Reference Manual," ver. 2.3, 2004.
-
-
-
-
20
-
-
33847738679
-
-
Available
-
[Online]. Available: www.xilinx.com
-
-
-
-
21
-
-
0343826160
-
RT-Level ITC'99 benchmarks and first ATPG results
-
Jul.-Aug
-
F. Corno, M. Sonza Reorda, and G. Squillero, "RT-Level ITC'99 benchmarks and first ATPG results," IEEE Des. Test Comput., pp. 44-53, Jul.-Aug. 2000.
-
(2000)
IEEE Des. Test Comput
, pp. 44-53
-
-
Corno, F.1
Sonza Reorda, M.2
Squillero, G.3
-
22
-
-
33847728770
-
-
Available
-
[Online]. Available: www.opencores.org
-
-
-
|