Reliability analysis of logic circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 3, 2009, Pages 392-405

  Choudhury, Mihir R ^a   Mohanram, Kartik ^a  

^a Rice University   (United States)

Author keywords

Gate failures; Logic circuits; Reliability analysis

Indexed keywords

ALGORITHMS; BENCHMARKING; ELECTRIC NETWORK ANALYSIS; FAILURE ANALYSIS; QUALITY ASSURANCE; RELIABILITY ANALYSIS; SWITCHING CIRCUITS;

BENCHMARK CIRCUITS; CLOSED-FORM EXPRESSIONS; CORRELATION COEFFICIENTS; ELECTRONIC TECHNOLOGIES; EXPONENTIAL NUMBERS; FAN OUTS; GATE FAILURES; MULTIPLE GATES; POTENTIAL APPLICATIONS; SCALABLE ALGORITHMS; SIMULATION RESULTS; SINGLE GATES;

LOGIC CIRCUITS;

EID: 60749115118     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2009.2012530     Document Type: Conference Paper

References (22)

1. R. W. Keyes, "Fundamental limits of silicon technology," Proc. IEEE, vol. 89, no. 3, pp. 227-239, Mar. 2001.
2. J. D. Meindl, Q. Chen, and J. A. Davis, "Limits on silicon nanoelectronics for terascale integration," Science, vol. 293, no. 5537, pp. 2044-2049, Sep. 2001.
3. G. Bourianoff, "The future of nanocomputing," Computer, vol. 36, no. 8, pp. 44-53, Aug. 2003.
4. V. V. Zhirnov, R. K. Cavin, J. A. Hutchby, and G. 1. Bourianoff, "Limits to binary logic switch scaling-A Gedanken model," Proc. IEEE, vol. 91, no. 11, pp. 1934-1939, Nov. 2003.
5. M. A. Breuer, S. K. Gupta, and T. M. Mak, "Defect and error tolerance in the presence of massive numbers of defects," IEEE Des. Test Comput., vol. 21, no. 3, pp. 216-227, May/Jun. 2004.
6. J. von Neumann, "Probabilistic logics and the synthesis of reliable organisms from unreliable components," in Automata Studies, C. E. Shannon and J. McCarthy, Eds. Princeton, NJ: Princeton Univ. Press, 1956, pp. 43-98.
7. A. Sadek, K. Nikoliæ;, and M. Forshaw, "Parallel information and computation with restitution for noise-tolerant nanoscale logic networks," Nanotechnology, vol. 15, no. 1, pp. 192-210, Jan. 2004.
8. S. Krishnaswamy, G. Viamontes, I. Markov, and J. Hayes, "Accurate reliability evaluation and enhancement via probabilistic transfer matrices," in Proc. Des. Autom. Test Eur., 2005, pp. 282-287.
9. T. Rejimon and S. Bhanja, "Scalable probabilistic computing models using Bayesian networks," in Proc. Int. Midwest Symp. Circuits Syst., 2005, pp. 712-715.
10. I. Bahar, J. L. Mundy, and J. Chen, "A probabilistic-based design methodology for nanoscale computation," in Proc. Int. Conf. Comput.-Aided Des., 2003, pp. 480-486.
11. D. Bhaduri and S. Shukla, "Nanolab: A tool for evaluating reliability of defect-tolerant nano architectures," in Proc. Annu. Symp. VLSI, 2004, pp. 25-31.
12. B. Zhang, W.-S. Wang, and M. Orshansky, "FASER: Fast analysis of soft error susceptibility for cell-based designs," in Proc. Int. Symp. Quality Electron. Des., 2006, pp. 755-760.
13. M. Zhang and N. R. Shanbhag, "A soft error rate analysis (SERA) methodology." in Proc. Int. Conf. Comput.-Aided Des., 2004. pp. 111-118.
14. S. Almukhaizim, Y. Makris, Y.-S. Yang, and A. Veneris, "Seamless integration of SER in rewiring based design space exploration," in Proc. Int. Test Conf., 2006, pp. 1-9.
15. S. Krishnaswamy, S. Plaza, I. Markov, and J. Hayes, "Enhancing design robustness with reliability-aware resynthesis and logic simulation," in Proc. Int. Conf. Comput.-Aided Des., 2007, pp. 149-154.
16. M. Choudhury and K. Mohanram, "Approximate logic circuits for low overhead, non-intrusive concurrent error detection," in Proc. Des. Autom. Test Eur., 2008, pp. 903-908.
17. M. Choudhury and K. Mohanram, "Accurate and scalable reliability analysis of logic circuits," in Proc. Des. Autom. Test Eur., 2007, pp. 1454-1459.
18. M. Nemani and F. Najm, "Towards a high-level power estimation capability," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 15, no. 6, pp. 588-598, Jun. 1996.
19. M. Damiani and G. De Micheli, "Observability don't care sets and Boolean relations," in Proc. Int. Conf. Comput.-Aided Des., 1990, pp. 502-505.
20. T. Larrabee, "Test pattern generation using Boolean satisfiability," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 11, no. 1, pp. 4-15, Jan. 1992.
21. S. Ercolani, M. Favalli, M. Damiani, P. Olivo, and B. Ricco, "Estimate of signal probability in combinational logic networks," in Proc. Eur. Test Conf., 1989, pp. 132-138.
22. G. Fishman, "Monte Carlo: Concepts, algorithms and applications," in Springer Series in Operations Research. New York: Springer-Verlag, 1995.