An autonomous SRAM with on-chip sensors in an 80nm double stacked cell technology

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn 2005, Issue , 2005, Pages 232-235

  Sohn, Kyomin ^a   Cho, Namjun ^a   Kim, Hyejung ^a   Kim, Kwanho ^a   Mo, Hyun Sun ^b   Suh, Young Ho ^b   Byun, Hyun Geun ^b   Yoo, Hoi Jun ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

Leakage current monitor; On chip timer; SRAM; Substrate noise; Temperature sensor

Indexed keywords

LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; SENSORS; SPURIOUS SIGNAL NOISE; SUBSTRATES;

LEAKAGE CURRENT MONITOR; ON-CHIP TIMER; SUBSTRATE NOISE; TEMPERATURE SENSOR;

RANDOM ACCESS STORAGE;

EID: 33745126679     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2005.1469374     Document Type: Conference Paper

References (3)

1. A. Kotabe, et.al., "A 0.13-um, 0.78-um2 Low-Power Four-Transistor SRAM Cell with a Vertically Stacked Poly-Silicon MOS and a Dual-Word-Voltage Scheme," Dig. Symp. VLSI Circuits, pp. 60-63, June 2004.
2. 2, and SSTFT (Stacked Single-crystal Thin Film Transistor) for Ultra High Density SRAM," Dig. Symp. VLSI Technology, pp. 228-229, June 2004.
3. K. Makie-Fukuda, T. Tsukada, "On-chip active guard band filters to suppress substrate-coupling noise in analog and digital mixed-signal integrated circuits," Dig. Symp. VLSI Circuits, pp. 57-60, June 1999.