A low-swing signaling circuit technique for 65nm on-chip interconnects

2006 IEEE International Systems-on-Chip Conference, SOC

Volumn , Issue , 2006, Pages 289-292

  Venkatraman, Vishak ^a   Anders, Mark ^b   Kaul, Himanshu ^b   Burleson, Wayne ^a   Krishnamurthy, Ram ^b  

^a University of Massachusetts   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ENERGY EFFICIENCY; NETWORKS (CIRCUITS);

GLOBAL INTERCONNECTS; LOW-SWING SIGNALING CIRCUIT TECHNIQUE;

ELECTRIC POWER SYSTEM INTERCONNECTION;

EID: 43749090409     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2006.283900     Document Type: Conference Paper

References (5)

1. 2 SRAM Cell., IEEE International Electron Devices Meeting, Dec. 2004, pp: 657-660.
2. Bohr M.T., Interconnect Scaling-the Real Limiter to High Performance ULSI, IEEE International Electron Devices Meeting, 10(13), Dec. 1995, pp: 241-244.
3. Bannerjee K. et al., Power-optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs, IEEE Transactions on Electron Devices, 49(11), Nov. 2002, pp: 2001-2007.
4. Chung-Ping Chen et al, Noise-aware Repeater Insertion and Wire Sizing for On-chip Interconnect Using Hierarchical Moment-matching, Design Automation Conference, 1999, pp: 502-506.
5. Zhang H. et al., Low-swing On-chip Signaling Techniques: Effectiveness and Robustness, IEEE Transactions on VLSI Systems, 8(3), Jun. 2000, pp: 264-272.