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Volumn , Issue , 2004, Pages 169-172

On-chip signaling for ultra low-voltage 0.13 μm CMOS SOI technology

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CAPACITANCE; ELECTRIC INVERTERS; ELECTRIC POTENTIAL; OPTIMIZATION; SIGNAL PROCESSING;

EID: 14844297415     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (3)

References (9)
  • 1
    • 0025477321 scopus 로고
    • CMOS tapered buffer
    • August
    • N. C. Li et. al., "CMOS tapered buffer", IEEE Journal of Solid-State Circuits, vol. 25, no.4, August 1990, pp. 1005-1008
    • (1990) IEEE Journal of Solid-state Circuits , vol.25 , Issue.4 , pp. 1005-1008
    • Li, N.C.1
  • 3
    • 34548823421 scopus 로고    scopus 로고
    • Fast signal propagation for point to point on-chip long interconnects using current sensing
    • A. Katoch et.al., "Fast Signal Propagation for Point to Point On-Chip Long Interconnects Using Current Sensing", ESSCIRC 2002
    • ESSCIRC 2002
    • Katoch, A.1
  • 4
    • 0026953436 scopus 로고
    • A 7ns 140mW 1Mb CMOS SRAM with current sense amplifier
    • November
    • K. Sasaki et. al, "A 7ns 140mW 1Mb CMOS SRAM with Current Sense Amplifier", IEEE Journal of Solid-State Circuits, vol. 27, no. 11, November 1992, pp. 1511-1518
    • (1992) IEEE Journal of Solid-state Circuits , vol.27 , Issue.11 , pp. 1511-1518
    • Sasaki, K.1
  • 5
    • 0026853678 scopus 로고
    • A high-speed sensing scheme for IT dynamic RAM's utilizing the clamped bit-line sense amplifier
    • April
    • T. Blalock et. al., "A High-Speed Sensing Scheme for IT Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier", IEEE Journal of Solid-State Circuits, vol. 27, no. 4, April 1992, pp. 618-625
    • (1992) IEEE Journal of Solid-state Circuits , vol.27 , Issue.4 , pp. 618-625
    • Blalock, T.1
  • 6
    • 0030121501 scopus 로고    scopus 로고
    • A current direction sense technique for mulitport SRAM's
    • April
    • M. Izumikawa et. al., "A current Direction Sense Technique for Mulitport SRAM's", IEEE Journal of Solid-State Circuits, vol. 31, no. 4, April 1996, pp.546-551
    • (1996) IEEE Journal of Solid-state Circuits , vol.31 , Issue.4 , pp. 546-551
    • Izumikawa, M.1
  • 7
    • 0036612248 scopus 로고    scopus 로고
    • A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell
    • June
    • N. Shibata et. al., "A Current-Sensed High-Speed and Low-Power First-In-First-Out Memory Using a Wordline/Bitline-Swapped Dual-Port SRAM Cell", IEEE Journal of Solid-State Circuits, vol. 37, no. 6, June 2002, pp. 735-750
    • (2002) IEEE Journal of Solid-state Circuits , vol.37 , Issue.6 , pp. 735-750
    • Shibata, N.1
  • 8
    • 0026141225 scopus 로고
    • Current-mode techniques for high-speed VLSI circuits with applications to current sense amplifier for CMOS SRAM's
    • April
    • Evert Seevinck, Petrus J. van Beers and Hans Ontrop, "Current-Mode Techniques for High-Speed VLSI Circuits with Applications to Current Sense Amplifier for CMOS SRAM's", IEEE Journal of Solid State Circuits, Vol. 26, No. 6, April 1991, pp. 525-536
    • (1991) IEEE Journal of Solid State Circuits , vol.26 , Issue.6 , pp. 525-536
    • Seevinck, E.1    Van Beers, P.J.2    Ontrop, H.3
  • 9
    • 0030219434 scopus 로고    scopus 로고
    • Current sense amplifiers for low-voltage memories
    • August
    • Nobutaro Shibata, "Current Sense Amplifiers for Low-Voltage Memories", IEICE Trans. Electron., Vol. E79-C, No. 8, August 1996, pp. 1120-1130
    • (1996) IEICE Trans. Electron. , vol.E79-C , Issue.8 , pp. 1120-1130
    • Shibata, N.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.