Two-phase resonant clock distribution

Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI

Volumn , Issue , 2005, Pages 65-70

  Chueh, Juang Ying ^a   Papaefthymiou, Marios C ^a   Ziesler, Conrad H ^b  

^a The Department of Civil and Environmental Engineering   (United States)

^b MultiGig Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK GENERATOR; INDUCTOR PARAMETERS; RESONANT CLOCK DISTRIBUTION; TUNABLE CAPACITORS;

CAPACITORS; COMPUTER SIMULATION; COPPER; ELECTRIC INDUCTORS; ENERGY DISSIPATION; JITTER; PRODUCT DESIGN;

RESONANT CIRCUITS;

EID: 26844488931     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2005.74     Document Type: Conference Paper

References (7)

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2. S. Chan, P. Restle, K. Shepard, N. James, and R. Franch. A 4.6GHz resonant global clock distribution network. In Proceedings of IEEE International Solid-State Circuits Conference, volume 1, Feb. 2004.
3. J. Denker, A. Dickinson, A. Kramer, and T. Wik. Low power-clock circuit. US patent 5559463.
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