FPGA technology for multi-axis control systems

Mechatronics

Volumn 19, Issue 2, 2009, Pages 258-268

  Astarloa, Armando ^a   Lázaro, Jesús ^a   Bidarte, Unai ^a   Jiménez, Jaime ^a   Zuloaga, Aitzol ^a  

^a UNIVERSITY OF THE BASQUE COUNTRY UPV EHU   (Spain)

Author keywords

Dynamic reconfiguration; FPGA; Motor control; PID; SoC

Indexed keywords

CONTROL SYSTEMS; CONTROLLERS; DYNAMIC MODELS; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTELLECTUAL PROPERTY CORE; REUSABILITY;

DYNAMIC RE-CONFIGURATION; MOTOR CONTROL; MOTOR CONTROLLERS; MULTI AXIS CONTROL; RUN TIME RECONFIGURATION; SELF-RECONFIGURABLE; SYSTEM ON A PROGRAMMABLE CHIPS; TRAJECTORY GENERATION;

SYSTEM-ON-CHIP;

EID: 58249142971     PISSN: 09574158     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mechatronics.2008.09.001     Document Type: Article

References (50)

1. Chang H et al. Surviving the SOC revolution, Kluwer Academic Publishers, Massachusetts, USA; 1999.
2. In: Martin G., and Chang H. (Eds). Winning the SoC revolution: experiences in real design (2003), Kluwer Academic Publishers, Massachusetts, USA
3. MacBeth J, Lysaght P. Dynamically reconfigurable intelectual property. In: Proceedings of the postgraduate research in electronics, photonics, communications and software (PREP'01); 2001.
4. Blodget B., James-Roxby P., Keller E., McMillan S., and Sundararajan P. A self-reconfiguring platform. Lecture Notes Comput Sci 2778 (2003) 565-574
5. Ullmann M., Hübner M., Grimm B., and Becker J. On-demand FPGA run-time system for dynamical reconfiguration with adaptive priorities. Lecture Notes Comput Sci 3203 (2004) 454-463
6. Astarloa A., Lázaro J., Bidarte U., Martín J.L., and Zuloaga A. A self-reconfiguration framework for multiprocessor CSoPCs. Lecture Notes Comput Sci 3203 (2004) 1124-1126
7. Hübner M., Ullmann M., Braun L., Klausmann A., and Becker J. Scalable application-dependent network on chip adaptivity for dynamical reconfigurable real-time systems. Lecture Notes Comput Sci 3203 (2004) 1037-1041
8. Kjosavik G. Take electronic motor drives to the next level. Embedded Mag 2 (2005) 34-37
9. Samet L, Masmoudi N, Kharrat M, Kamoun L. A digital PID controller for real time and multi loop control: a comparative study. In: Proceedings of the 1998 IEEE international conference on electronics, circuits and systems; 1998. p. 291-6.
10. Chen R., Chen L., and Chen L. System design consideration for digital wheelchair controller. IEEE Trans Ind Electron 47 4 (2000) 898-907
11. Zhao W, Kim BH, Larson AC, Voyles R. FPGA implementation of closed-loop control system for small-scale robot. In: Proceedings of the 12th international conference on advanced robotics ICAR; 2005.
12. Bucella T. Servo control of a DC-brush motor. Application note AN532, MICROCHIP; 1997.
13. Afghahi M., and Svensson C. Performance of synchronous and asyncronous schemes for VLSI systems. IEEE Trans Comput 41 7 (1992) 858-872
14. Ogata K. Modern control engineering (1997), Prentice Hall
15. Xilinx Corp. Using embedded multipliers in Spartan-3 FPGAs, Xilinx application notes, ; 2003.
16. National Semiconductor. LMD18245 3A, 55V DMOS full-bridge motor driver datasheet, .
17. S. Corporation. Wishbone system-on-chip (SoC) interconnection architecture for portable IP cores revision: B.3, ; 2002.
18. The MathWorks. Simulink, .
19. Xilinx Corp. System generator for DSP, .
20. Mentor Graphics. ModelSim, .
21. Gupta Y.Z.R.K. Introducing core-based system design. IEEE Des Test Comput 14 4 (1997) 15-25
22. Bergamaschi R.A., Bhattacharya S., Wagner R., Fellenz C., and Muhlada M. Automating the design of SOCs using cores. IEEE Des Test Comput 18 5 (2001) 32-45
23. Compton K., and Hauck S. Reconfigurable computing: a survey of systems and software. ACM Comput Surv 34 2 (2002) 171-210
24. Waller L. The big question in counting FPGA gates: should memory be included, EE times online, .
25. Xilinx Corp. Digital clock manager (DCM) module, .
26. ™ soft processor core, Xilinx processor central, ; 2008.
27. I. IBM. Coreconnect Spec., IBM web site: ; 2003.
28. Astarloa A, Sáiz P, Lázaro J, Jacob E, Bidarte U. Multi-architectural 128 bit AES-CBC core based on open-source hardware AES implementations for secure industrial communications. In: Proceedings of the 10th international conference on communication technology (ICCT2006); 2006. p. 221-6.
29. Sáiz P. A model for establishing secure sessions at the link layer between endpoints in ethernet networks. PhD thesis, Faculty of Engineeering. UPV/EHU; 2007.
30. Xilinx Corp. Spartan-3 complete datasheet, Xilinx Documentation, ; 2005.
31. Compton K., Li Z., Cooey J., Knol S., and Hauck S. Configuration relocation and defragmentation for run-time reconfigurable computing. IEEE Trans VLSI Syst 10 3 (2002) 209-220
32. Guccione S.A., and Levi D. Run-time parametrizable cores. Lecture Notes Comput Sci 1673 (1999) 215-222
33. Hadley J, Hutchings B. Design methodologies for partially reconfigured systems. In: Proceedings of the IEEE symposium on field-programmable custom computing machines (FCCM'95); 1995. p. 78-84.
34. Dyer M, Wirz M. Reconfigurable system on FPGA, Computer engineering. Master thesis, Swiss Federal Institute of Technology Zurich; 2002.
35. Astarloa A. Dynamic partial reconfiguration of multi-processor modular systems in sopc devices. PhD thesis, University of the Basque Country; 2005.
36. Enzel R., Plessl C., and Plazer M. Virtualizing hardware with multi-context reconfigurable arrays. Lecture Notes Comput Sci 2778 (2003) 151-160
37. Xilinx Corp. Two flows for partial reconfiguration: module based or small bit manipulations. Xilinx Application Notes, ; 2002.
38. Xilinx Corp. PlanAhead design analysis tool, ; 2008.
39. Horta EL, Lockwood JW, Taylor DE, Parlour D. Dynamic hardware plugins in an FPGA with partial run-time reconfiguration. In: Proceedings of the design automation conference (DAC'02), New Orleans, LA; 2002. p. 343-8.
40. Fong RJ, Harper SJ, Athanas PM. A versatile framework for FPGA field updates: an application of partial self-reconfiguration. In: Proceedings of the 14th IEEE international workshop on rapid systems prototyping (RSP'03); 2003. p. 117-23.
41. Xilinx Corp. ISE8.1 Xilinx libraries guide, ; 2007.
42. Danne K., Bobda C., and Kalte H. Run-time exchange of mechatronic controllers using partial hardware reconfiguration. Lecture Notes Comput Sci 2778 (2003) 272-281
43. APERT, Applied Electronics Research Team, Universidad del País Vasco, (2004).
44. Astarloa A., Zuloaga A., Bidarte U., Martín J.L., Jiménez J., and Lázaro J. Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs. J Syst Arch 53 9 (2007) 629-643
45. Sidhu R., and Prasanna V. Efficient metacomputation using self-reconfiguration. Lecture Notes Comput Sci 2438 (2002) 698-709
46. Brebner G., and Donlin A. Runtime reconfigurable routing. Lecture Notes Comput Sci 1388 (1998) 25-30
47. Astarloa A, Bidarte U, Jiménez J, Arias J, Kortabarría I. Wishbone compatible bus-macro for inter-task partial reconfiguration. In: Proceedings of the Jornadas de Computación Reconfigurable y Aplicaciones (JCRA'05), University of Granada; 2005. p. 17-24.
48. Xilinx Corp. ISE 6.1 Xilinx libraries guide, ; 2003.
49. Logue J. XAPP155: Virtex analog to digital converter, Xilinx application notes, ; 1999.
50. Lysaght P. Aspects of dynamically reconfigurable logic, IEE coloquium on reconfigurable systems; 1999.