Virtualizing hardware with multi-context reconfigurable arrays

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2778, Issue , 2003, Pages 151-160

  Enzler, Rolf ^a   Plessl, Christian ^a   Platzner, Marco ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; HARDWARE; RECONFIGURABLE ARCHITECTURES; VIRTUAL REALITY;

COARSE-GRAINED RECONFIGURABLE ARRAYS; CONTEXT ARCHITECTURE; CYCLE-ACCURATE SIMULATION; FORWARD COMPATIBILITY; HARDWARE IMPLEMENTATIONS; HARDWARE VIRTUALIZATION; RECONFIGURABLE ARRAY; RECONFIGURABLE DEVICES;

RECONFIGURABLE HARDWARE;

EID: 35248857952     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-45234-8_16     Document Type: Article

References (10)

1. Goldstein, S.C., Schmit, H., Budiu, M., Cadambi, S., Moe, M., Taylor, R.R.: PipeRench: A reconfigurable architecture and compiler. IEEE Computer 33 (2000) 70-77
2. Trimberger, S., Carberry, D., Johnson, A., Wong, J.: A time-multiplexed FPGA. In: Proc. 5th IEEE Symp. on Field-Programmable Custom Computing Machines (FCCM). (1997) 22-28
3. Caspi, E., Chu, M., Huang, R., Yeh, J., Wawrzynek, J., DeHon, A.: Stream computations organized for reconfigurable execution (SCORE). In: Field-Programmable Logic and Applications (Proc. FPL), LNCS 1896, Springer-Verlag (2000) 605-614
4. Schmit, H., Whelihan, D., Moe, M., Levine, B., Taylor, R.R.: PipeRench: A virtualized programmable datapath in 0.18 micron technology. In: Proc. 24th IEEE Custom Integrated Circuits Conf. (CICC). (2002) 63-66
5. DeHon, A.: DPGA utilization and application. In: Proc. 4th ACM Int. Symp. on Field-Programmable Gate Arrays (FPGA). (1996) 115-121
6. Baumgartne, V., May, F., Nückel, A., Vorbach, M., Weinhardt, M.: PACT XPP - a self-reconfigurable data processing architecture. In: Proc. 1st Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). (2001) 64-70
7. Singh, H., Lee, M.H., Lu, G., Kurdahi, F.J., Bagherzadeh, N., Chaves Filho, E.M.: MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications. IEEE Trans. on Computers 49 (2000) 465-481
8. Enzler, R., Plessl, C., Platzner, M.: Co-simulation of a hybrid multi-context architecture. In: Proc. 3rd Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). (2003)
9. Hauser, J.R., Wawrzynek, J.: Garp: A MIPS processor with a reconfigurable co-processor. In: Proc. 5th IEEE Symp. on Field-Programmable Custom Computing Machines (FCCM). (1997) 12-21
10. Austin, T., Larson, E., Ernst, D.: SimpleScalar: An infrastructure for computer system modeling. IEEE Computer 35 (2002) 59-67