Using analytical models to efficiently explore hardware transactional memory and multi-core co-design

Proceedings - Symposium on Computer Architecture and High Performance Computing

Volumn , Issue , 2008, Pages 159-166

  Poe, James ^a   Cho, Chang Burm ^a   Li, Tao ^a  

^a University of Florida

Author keywords

[No Author keywords available]

Indexed keywords

ACCURATE PERFORMANCES; ANALYTICAL MODELING; ANALYTICAL MODELS; APPLICATION SPECIFICS; BUILDING METHODS; CO DESIGNS; CORE CONFIGURATIONS; CORE DESIGNS; CORE PROCESSORS; DESIGN DIMENSIONS; EFFECTIVE TOOLS; HARDWARE TRANSACTIONAL MEMORIES; HETEROGENEOUS INTERACTIONS; HIGH IMPACTS; KEY FEATURES; LARGE DESIGNS; MICROARCHITECTURAL PARAMETERS; MICROARCHITECTURE; MICROARCHITECTURES; MODELING TECHNIQUES; NEURAL NETWORK MODELS; PARALLEL PROGRAMMING PARADIGMS; PERFORMANCE MODELS; REGRESSION TREES; TRANSACTIONAL MEMORIES;

COMPUTER SIMULATION; COMPUTERS; DESIGN; FLOW INTERACTIONS; HIGH PERFORMANCE LIQUID CHROMATOGRAPHY; MARKUP LANGUAGES; MICROPROCESSOR CHIPS; NEURAL NETWORKS; PARALLEL PROCESSING SYSTEMS; PARALLEL PROGRAMMING; STORAGE ALLOCATION (COMPUTER);

COMPUTER ARCHITECTURE;

EID: 58049190386     PISSN: 15506533     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBAC-PAD.2008.18     Document Type: Conference Paper

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