Characterization of TCC on chip-multiprocessors

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn 2005, Issue , 2005, Pages 63-74

  McDonald, Austen ^a   Chung, Jaewoong ^a   Chafi, Hassan ^a   Minh, Chi Cao ^a   Carlstrom, Brian D ^a   Hammond, Lance ^a   Kozyrakis, Christos ^a   Olukotun, Kunle ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PARALLEL APPLICATIONS; TRANSACTIONAL COHERENCE AND CONSISTENCY (TCC); WRITE-INVALIDATE PROTOCOLS;

BANDWIDTH; CACHE MEMORY; NETWORK PROTOCOLS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; STORAGE ALLOCATION (COMPUTER);

MICROPROCESSOR CHIPS;

EID: 33745221558     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2005.11     Document Type: Conference Paper

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