Design methodology of body-biasing scheme for low power system LSI with multi-Vth transistors

IEEE Transactions on Electron Devices

Volumn 54, Issue 11, 2007, Pages 2946-2951

  Yasuda, Yuri ^a,b   Akiyama, Yutaka ^a   Yamagata, Yasushi ^a   Goto, Yoshiro ^a   Imai, Kiyotaka ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Body biasing; Body factor; Buried channel; Gate leakage; Gate induced drain leakage (GIDL); HfSiON; High Vth; Low power; Multi th; Retrograde channel; Standby leakage; Variation

Indexed keywords

LEAKAGE CURRENTS; RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE; TRANSISTORS; WORK FUNCTION;

BODY BIASING; GATE-INDUCED DRAIN LEAKAGE;

LSI CIRCUITS;

EID: 36448950215     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.906964     Document Type: Article

References (16)

1. J. C. Lee, H. J. Cho, C. S. Kang, S. Rhee, Y. H. Kim, R. Choi, C. Y. Kang, C. Choi, and M. Abkar, "High-k dielectrics and MOSFET characteristics," in IEDM Tech. Dig., Dec. 2003, pp. 95-98.
2. S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El-Mansy, "A logic nanotechnology featuring strained-silicon," IEEE Electron Device Lett., vol. 25, no. 4, pp. 191-193, Apr. 2004.
3. M. Horowitz, E. Alon, D. Patil, S. Naffziger, R. Kumar, and K. Bernstein, "Scaling, power, and the future of CMOS," in IEDM Tech. Dig., Dec. 2005, pp. 9-15.
4. K. Takeuchi, R. Koh, and T. Mogami, "A study of the threshold voltage variation for ultra-small bulk and SOI CMOS," IEEE Trans. Electron Device, vol. 48, no. 9, pp. 1995-2001, Sep. 2001.
5. standby ratio and reliability," in VLSI Symp. Tech. Dig., 2004, pp. 40-41.
6. M. Togo, T. Fukai, Y. Nakahara, S. Koyama, M. Makabe, E. Hasegawa, M. Nagase, T.Matsuda, K. Sakamoto, S. Fujiwara, Y. Goto, T. Yamamoto, T. Mogami, M. Ikeda, Y. Yamagata, and K. Imai, "Power-aware 65 nm node CMOS technology using variable VDD and back-bias control with reliability consideration for back-bias mode," in VLSI Symp. Tech. Dig., 2004, pp. 88-89.
7. A. Keshavarzi, S. Narendra, B. Bloechel, S. Borkar, and V. De, "Forward body bias for microprocessors in 130 nm technology generation and beyond," in VLSI Symp. Tech. Dig., 2002, pp. 312-315.
8. N. Kimizuka, Y. Yasuda, T. Iwamoto, I. Yamamoto, K. Takano, Y. Akiyama, and K. Imai, "Ultra-low standby power (U-LSTP) 65-nm node CMOS technology utilizing HfSiON dielectric and body-biasing scheme," in VLSI Symp. Tech. Dig., 1999, pp. 218-219.
9. Y. Shimamoto, J. Yugami, M. Inoue, M. Mizutani, T. Hayashi, K. Shiga, F. Fujita, M. Yoneda, and H. Matsuoka, "Advantages of gate workfunction engineering by incorporating sub-monolayer Hf at SiON/poly-Si interface in low-power CMOS," in VLSI Symp. Tech. Dig., 2005, pp. 132-133.
10. C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White, and P. Tobin, "Fermi level pinning at the poly-Si/metal oxide interface," in VLSI Symp. Tech. Dig., 2003, pp. 9-10.
11. International Technology Roadmap for Semiconductors, 2004.
12. R. W. Keyes, "The effect of randomness in the distribution of impurity atoms on FET thresholds," Appl. Phys., vol. 8, no. 3, pp. 251-259, Nov. 1975.
13. T. Mizuno, J. Okamura, and A. Toriumi, "Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFETs," IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 2216-2221, Nov. 1994.
14. K. Noda, T. Tatsumi, T. Uchida, K. Nakajima, H. Miyamoto, and C. Hu, "A 0.1-μm delta-doped MOSFET fabricated with post-low-energy implanting selective epitaxy," IEEE Trans. Electron Devices, vol. 45, no. 4, pp. 809-814, Apr. 1998.
15. K. Imai, Y. Yamagata, S. Masuoka, N. Kimizuka, Y. Yasuda, M. Togo, M. Ikeda, and Y. Nakashiba, "Device technology for body biasing scheme," in Proc. IEEE Int. Symp. Circuits Syst., May 2005, pp. 13-16.
16. H. C.-H.Wang, S. Chen, M.-F.Wang, P.-Y. Tsai, C.-W. Tsai, T.-W.Wang, M. Ting, T.-H. Hou, P.-S. Lim, H.-J. Lin, Y. Jin, H.-J. Tao, S.-C. Chen, C. H. Diaz, M.-S. Liang, and C. Hu, "Low power device technology with SiGe channel, HfSiON, and poly-Si gate," in IEDM Tech. Dig., Dec. 2004, pp. 161-164.