Pyramids: An efficient computational geometry-based approach for timing-driven placement

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2008, Pages 204-211

  Luo, Tao ^a,b   Papa, David A ^c,d   Li, Zhuo ^d   Sze, C N ^d   Alpert, Charles J ^d   Pan, David Z ^b  

^a MAGMA DESIGN AUTOMATION   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^c The Department of Civil and Environmental Engineering   (United States)

^d IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LINEAR PROGRAMMING SOLVERS; NEW TECHNIQUES; OPTIMAL LOCATIONS; OPTIMAL TIMINGS; PLACEMENT ALGORITHMS; SPEED-UP; TIMING INFORMATIONS; WIRE LENGTHS;

COMPUTATIONAL GEOMETRY; COMPUTER AIDED DESIGN; DYNAMIC PROGRAMMING; LINEARIZATION; LOCATION; PARTICLE SIZE ANALYSIS;

TIME MEASUREMENT;

EID: 57849164044     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2008.4681575     Document Type: Conference Paper

References (18)

1. B. Halpin, C. Y. R. Chen, and N. Sehgal, "Timing driven placement using physical net constraints," in Proc. Design Automation Conf., pp. 780-783, 2001.
2. T. T. Kong, "A novel net weighting algorithm for timing-driven placement," in Proc. Int. Conf. on Computer Aided Design, pp. 172-176, 2002.
3. H. Ren, D. Z. Pan, and D. S. Kung, "Sensitivity guided net weighting for placement driven synthesis.," in Proc. Int. Symp. on Physical Design, pp. 10-17, 2004.
4. W. Choi and K. Bazargan, "Incremental placement for timing optimization," in Proc. Int. Conf. on Computer Aided Design, p. 463, 2003.
5. Q. B. Wang, J. Lillis, and S. Sanyal, "An lp-based methodology for improved timing-driven placement," in Proc. Asia and South Pacific Design Automation Conf., 2005.
6. A. Chowdhary, K. Rajagopal, S. Venkatesa, T. Cao, V. Tiourin, Y. Parasuram, and B. Halpin, "How accurately can we model timing in a placement engine?," in Proc. Design Automation Conf., pp. 801-806, 2005.
7. T. Luo, D. Newmark, and D. Z. Pan, "A new LP based incremental timing driven placement for high performance designs," in Proc. Design Automation Conf., 2006.
8. D. Papa, T. Luo, M. D. Moffitt, C. N. Sze, Z. Li, G.-J. Nam, C. Alpert, and I. Markov, "Rumble: An incremental, timing-driven physical -synthesis optimization algorithm," in Proc. Int. Symp. on Physical Design, 2008.
9. COIN-OR linear programming, "https://projects.coin-or.org/clp,"
10. GNU Linear Programming Kit, "http://www.gnu.org/software/glpk/, "
11. R. Otten, "Global wires harmful?," in Proc. Int. Symp. on Physical Design, pp. 104-109, Apr. 1998.
12. C. J. Alpert and et.al., "Accurate estimation of global buffer delay within a floorplan," in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2006.
13. J. Cong, L. He, C.-K. Koh, and P. H. Madden, "Performance optimization of VLSI, interconnect layout," Integration, the VLSI Journal, vol. 21, pp. 1-94, 1996.
14. P. C. P. Saxena, N. Menezes and D. A. Kirkpatrick, "Repeater scaling and its impact on cad," in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2004.
15. OpenAccess, "http://openeda.si2.org/,"
16. Z. Xiu, D. A. Papa, and et.al., "Early research experience with OpenAccess gear: an open source development environment for physical design," in Proc. Int. Symp. on Physical Design, 2005.
17. OAGear:, "http://openedatools.si2.org/oagear/,"
18. C. J. Alpert and et al., "Fast and flexible buffer trees that navigate the physical layout environment," in Proc. Design Automation Conf., 2004.