-
3
-
-
0030108013
-
Retiming revisited and reversed
-
March
-
G. Even, I. Y. Spillinger, and L. Stok, "Retiming revisited and reversed," IEEE Transactions on Computer-Aided Design, vol. 15, pp. 348-357, March 1996.
-
(1996)
IEEE Transactions on Computer-Aided Design
, vol.15
, pp. 348-357
-
-
Even, G.1
Spillinger, I.Y.2
Stok, L.3
-
4
-
-
0346868084
-
Chip clocking effect on performace for IBM's SA-27E ASIC technology
-
K. M. Carrig, "Chip clocking effect on performace for IBM's SA-27E ASIC technology," IBM Micronews, vol. 6, no. 3, pp. 12-16, 2000.
-
(2000)
IBM Micronews
, vol.6
, Issue.3
, pp. 12-16
-
-
Carrig, K.M.1
-
5
-
-
0034852165
-
Chaff: Engineering an efficient SAT solver
-
Las Vegas, Nevada, June
-
M. W. Moskewicz, C. F. Madigan, Y. Zhao, L. Zhang, and S. Malik, "Chaff: Engineering an efficient SAT solver," in Proceedings of the 38th ACM/IEEE Design Automation Conference, (Las Vegas, Nevada), pp. 530-535, June 2001.
-
(2001)
Proceedings of the 38th ACM/IEEE Design Automation Conference
, pp. 530-535
-
-
Moskewicz, M.W.1
Madigan, C.F.2
Zhao, Y.3
Zhang, L.4
Malik, S.5
-
6
-
-
0003681232
-
-
PhD thesis, California Institute of Technology, Pasadena, CA, December
-
S. M. Burns, Performance Analysis and Optimization of Asynchronous Circuits. PhD thesis, California Institute of Technology, Pasadena, CA, December 1991.
-
(1991)
Performance Analysis and Optimization of Asynchronous Circuits
-
-
Burns, S.M.1
-
9
-
-
0033348306
-
Cycle time and slack optimization for vlsi-chips
-
November
-
C. Albrecht, B. Korte, J. Schietke, and J. Vygen, "Cycle time and slack optimization for vlsi-chips," in Digest of Technical Papers of the IEEE International Conference on Computer-Aided Design, pp. 232-238, November 1999.
-
(1999)
Digest of Technical Papers of the IEEE International Conference on Computer-Aided Design
, pp. 232-238
-
-
Albrecht, C.1
Korte, B.2
Schietke, J.3
Vygen, J.4
-
10
-
-
84986979889
-
Faster parametric shortest path and minimum balance algorithms
-
N. E. Young, R. E. Tarjan, and J. B. Orlin, "Faster parametric shortest path and minimum balance algorithms," Networks, vol. 21, no. 2, pp. 205-221, 1991.
-
(1991)
Networks
, vol.21
, Issue.2
, pp. 205-221
-
-
Young, N.E.1
Tarjan, R.E.2
Orlin, J.B.3
-
11
-
-
0033701747
-
A practical clock tree synthesis for semi-synchronous circuits
-
M. Toyonaga, K. Kurokawa, T. Yasui, and A. Takahashi, "A practical clock tree synthesis for semi-synchronous circuits," in Proceedings of the 2000 International Symposium on Physical Design, pp. 159-164, 2000.
-
(2000)
Proceedings of the 2000 International Symposium on Physical Design
, pp. 159-164
-
-
Toyonaga, M.1
Kurokawa, K.2
Yasui, T.3
Takahashi, A.4
-
13
-
-
0003101648
-
Sequential circuit design using synthesis and optimization
-
E. Sentovich, K. Singh, C. Moon, H. Savoj, R. Brayton, and A. Sangiovanni-Vincentelli, "Sequential circuit design using synthesis and optimization," in Proc. of the Internat. Conf. on Computer Design (ICCD'92), pp. 328-333, 1992.
-
(1992)
Proc. of the Internat. Conf. on Computer Design (ICCD'92)
, pp. 328-333
-
-
Sentovich, E.1
Singh, K.2
Moon, C.3
Savoj, H.4
Brayton, R.5
Sangiovanni-Vincentelli, A.6
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