Word-interleaved cache: An energy efficient data cache architecture

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2008, Pages 265-270

  Kalyan, T Venkata ^a   Mutyam, Madhu ^b  

^a INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY   (India)

^b INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

Author keywords

Cache; Low power technique; Offset based decoding

Indexed keywords

CACHE MEMORY; DECODING; ENERGY EFFICIENCY; LOW POWER ELECTRONICS;

AREA OVERHEADS; CACHE; CACHE ACCESS; CACHE BLOCKS; DATA CACHES; DYNAMIC ENERGIES; ENERGY-EFFICIENT; LOW-POWER TECHNIQUE; OFFSET BASED DECODING; PERFORMANCE DEGRADATIONS; SET ASSOCIATIVE CACHES;

POWER ELECTRONICS;

EID: 57649111387     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1393921.1393991     Document Type: Conference Paper

References (27)

1. SimpleScalar toolset. http://www.simpIeKcalar.com.
2. SPEC 2000 Benchmark. http://www.spcc.org.
3. D. Albonesi, "Selective cache ways: on-demand cache resource allocation". International Symposium, on Microarchitecture, 1999, pp. 248-259.
4. B. Batson and T. N. Vijaykumar. "Reactive-associative caches". Inter-national Conference on Parallel Architectures and Compilation Techniques. 2001, pp. 49-60.
5. B. Cadler, et.al., "Predictive sequential associative cache". International Symposium on High Performance Computer- Architecture, 1996, pp. 244-253.
6. Y. Chang and F. Lai, "Dynamic zero-sensitivity scheme for low-power cache memories". IEEE Micro. 25(4), 2005. pp. 20-32.
7. Y. Chang, et.al., "Design and analysis of low-power cache using two-level filter scheme". IEEE Transactions on Very Large Scale Integration Systems, 11(4), 2003, pp. 568-580.
8. D. Brooks, et.al., "Wattch: a framework for architectural-level power analysis and optimizations". International Symposium on Computer Architecture, 2000, pp. 83-94.
9. K. Ghose and M. B. Kamble, "Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation". International Symposium on Low Power Electronics and Design. 1999, pp. 306-315.
10. E. Gibert, J. Sánchez, A. Gonzalez. "Effective Instruction Scheduling Techniques for an Interleaved Cache Clustered VLIW Processor". IEEE Micro, 2002, pp. 123-133.
11. A. Hasegawa, et.al., "SH3: high code density, low power". IEEE Micro, 15(6), 1995, pp. 11-19.
12. L. Hennessey and D. A. Patterson, Computer Architecture: A Quantitative Approach. 4th Edition. Elsevier Science & Technology Books, 2006.
13. M. Huang, et.al., "L1 data cache decomposition for energy efficiency". International Symposium on Low Power Electronics and Design, 2001, pp. 10-15.
14. K. Inoue, et.al., "Way-predicting set-associative cache for high performance and low energy consumption". International Symposium on Low Power Electronics and Design, 1999, pp. 273-275.
15. P. Jung-Wook, et.al., "Powcr-aware deterministic block allocation for low-power way-selective cache structure". International Conference on Computer Design, 2004, pp. 42-47.
16. S. Kaxiras, et.al., "Cache decay: exploiting generational behavior to reduce cache leakage power". ACM SIGARCH Computer Architecture News, 29(2), 2001, pp. 240-251.
17. C. Kim, D. Burger and S. W. Kecklcr, "An Adaptive, NonUniform Cache Structure for WireDelay Dominated OnChip Caches". ASPLOS, 2002, pp. 211-222.
18. J. Kin, et.al., "The filter cache: an energy efficient memory structure". International Symposium on Microarchitecture, 1999, pp. 184-193.
19. G. Memik, et.al., "Reducing energy and delay using efficient victim caches". International Symposium on Low Power Electronics and, Design, 2003, pp. 262-265.
20. J. Montanaro, et.al., "A 160 MHz, 32b 0.5W CMOS RISC microprocessor". International Solid-State Circuits Conference, 1996, pp. 214-215.
21. D. Nicolaescu, et.al., "Reducing data cache energy consumption via cached load/store queue". International Symposium on Low Power Electronics and Design, 2003, pp. 252-257.
22. P. Petrov and A. Orailoglu, "Tag compression for low power in dynamically customizable embedded processors". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(7), 2004, pp. 1031-1047.
23. D. Tarjan, S. Thoziyoor and N. Jouppi, "CACTI 4.0: An Integrated Cache Timing, Power and Area Model", Technical report, HP Laboratories Palo Alto. June 2006.
24. C. Su and A. Despain, "Cache design tradeoff's for power and performance optimizations: a case study". International Symposium on Low Power Electronics and Design, 1995, pp. 63-68.
25. C. Zhang, et.al., "A way-halting cache for low-energy high-performance systems". ACM Trans actions on Architecture and Code Optimization, 2005, pp. 34-54.
26. M. Zhang, et.al., "Reducing cache energy consumption by tag encoding in embedded processors". International Symposium on Low Power Electronics and Design, 2007, pp. 367-370.
27. Z. Zhang and X. Zhang, "Access-mode predictions for low-power cache design". IEEE Micro, 22(2), 2002, pp. 58-71.