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Volumn , Issue , 2007, Pages 367-370

Reducing cache energy consumption by tag encoding in embedded processors

Author keywords

Cache; Embedded processors; Low power design; Tag encoding

Indexed keywords

BLOCK BUFFERING; COLUMN ACTIVATION; DATA ACCESSES; EMBEDDED PROCESSORS; LOW POWER DESIGN; TAG ENCODING;

EID: 36949018665     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1283780.1283860     Document Type: Conference Paper
Times cited : (12)

References (17)
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    • Chia-Lin Yang; Chicn-Hao Lee; "HotSpot Cache: Joint Temporal and Spatial Locality Exploitation for I-Cache Energy Reduction", Low Power Electronics and Design, 2004. ISLPED'04. Proceedings of the 2004 International Symposium on, 9-11 Aug. 2004 Page(s):114 - 119
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    • Inoue, K.; Ishihara, T.; Murakami, K.; Way-predicting setassociative cache for high performance and low energy consumption. Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on, 1999 Page(s):273 - 275
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.