-
1
-
-
24644449827
-
Effect of post development process for resist roughness
-
K. Sho, T. Shibata, E. Shiobara, S. Ito, "Effect of post development process for resist roughness", Proc. SPIE 5753, 405-407 (2005)
-
(2005)
Proc. SPIE
, vol.5753
, pp. 405-407
-
-
Sho, K.1
Shibata, T.2
Shiobara, E.3
Ito, S.4
-
2
-
-
24644514810
-
Effect of Hardbake Process on LWR
-
M. Padmanaban, D. Rentkiewicz, S. Lee, C. Hong, D. Lee, D. Rahman, R. Sakamuri, R. Dammel, "Effect of Hardbake Process on LWR", Proc. SPIE 5753, 862-868 (2005)
-
(2005)
Proc. SPIE
, vol.5753
, pp. 862-868
-
-
Padmanaban, M.1
Rentkiewicz, D.2
Lee, S.3
Hong, C.4
Lee, D.5
Rahman, D.6
Sakamuri, R.7
Dammel, R.8
-
3
-
-
33745620488
-
LWR Reduction in ArF Resist pattern by Resist smoothing process
-
61533X-1-61533X-9
-
Y. Inatomi, T. Kawasaki, M. Iwashita, "LWR Reduction in ArF Resist pattern by Resist smoothing process", Proc. SPIE 6153, 61533X-1-61533X-9 (2006)
-
(2006)
Proc. SPIE
, vol.6153
-
-
Inatomi, Y.1
Kawasaki, T.2
Iwashita, M.3
-
4
-
-
3843130605
-
Effect of line edge roughness (LER) and line width roughness (LWR) on Sub-100 nm Device Performance
-
J-Y. Lee, J. Shin, H-W Kim, S-G Woo, H-K Cho, W-S Han, J-T Moon, "Effect of line edge roughness (LER) and line width roughness (LWR) on Sub-100 nm Device Performance", Proc. SPIE 5376, 426-433 (2004)
-
(2004)
Proc. SPIE
, vol.5376
, pp. 426-433
-
-
Lee, J.-Y.1
Shin, J.2
Kim, H.-W.3
Woo, S.-G.4
Cho, H.-K.5
Han, W.-S.6
Moon, J.-T.7
-
5
-
-
4344603151
-
Metrology of LER: Influence of line-edge roughness (LER) on transistor performance
-
A. Yamaguchi, K. Ichinose, S. Shimamoto, H. Fukuda, R. Tsuchiya, K. Ohnishi, H. Kawada, T. Iizumi, " Metrology of LER: influence of line-edge roughness (LER) on transistor performance", Proc. SPIE 5375, 468-476 (2004)
-
(2004)
Proc. SPIE
, vol.5375
, pp. 468-476
-
-
Yamaguchi, A.1
Ichinose, K.2
Shimamoto, S.3
Fukuda, H.4
Tsuchiya, R.5
Ohnishi, K.6
Kawada, H.7
Iizumi, T.8
-
6
-
-
4344658756
-
Influence of line edge roughness on MOSFET devices with sub-50nm gates
-
K. Shibata, N. Izumi, K. Tsujita, "Influence of line edge roughness on MOSFET devices with sub-50nm gates", Proc. SPIE 5375, 865 (2004)
-
(2004)
Proc. SPIE
, vol.5375
, pp. 865
-
-
Shibata, K.1
Izumi, N.2
Tsujita, K.3
-
7
-
-
0035364688
-
An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling
-
C. H. Diaz et al, "An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling", IEEE Electron devices letters, 22(6), 287-289 (2001)
-
(2001)
IEEE Electron devices letters
, vol.22
, Issue.6
, pp. 287-289
-
-
Diaz, C.H.1
-
8
-
-
3843151399
-
Characterization of line edge roughness in photoresist using an image fading technique
-
A. R. Powloski, A. Acheta, I. Lalovic, B. La Fontaine, H. J. Levinson, "Characterization of line edge roughness in photoresist using an image fading technique", Proc. SPIE 5376, 414-425 (2004)
-
(2004)
Proc. SPIE
, vol.5376
, pp. 414-425
-
-
Powloski, A.R.1
Acheta, A.2
Lalovic, I.3
La Fontaine, B.4
Levinson, H.J.5
-
9
-
-
0141498380
-
ArF issues of 90nm node DRAM device integration
-
D-H Goo, B-S Kim, J-S Park, K-S Yoon, J-H Lee, H-K Cho, W-S Han, J-T Moon, "ArF issues of 90nm node DRAM device integration", Proc. SPIE 5040, 1296-1303 (2003)
-
(2003)
Proc. SPIE
, vol.5040
, pp. 1296-1303
-
-
Goo, D.-H.1
Kim, B.-S.2
Park, J.-S.3
Yoon, K.-S.4
Lee, J.-H.5
Cho, H.-K.6
Han, W.-S.7
Moon, J.-T.8
-
10
-
-
0141499413
-
Spatial Frequency Analysis of Line Edge Roughness in Nine Chemically Related Photoresists
-
W. G. Lawrence, "Spatial Frequency Analysis of Line Edge Roughness in Nine Chemically Related Photoresists", Proc. SPIE 5039, 713-724 (2003)
-
(2003)
Proc. SPIE
, vol.5039
, pp. 713-724
-
-
Lawrence, W.G.1
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