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Volumn 54, Issue 9, 2007, Pages 2526-2530

Highly reliable 90-nm logic multitime programmable NVM cells using novel work-function-engineered tunneling devices

Author keywords

Defect generation rate; Endurance; Multitime programmable (MTP); Nonvolatile memory (NVM); Stressinduced leakage current (SILC); Work function engineered

Indexed keywords

ELECTRON TUNNELING; EMBEDDED SYSTEMS; LEAKAGE CURRENTS; MANUFACTURE; WORK FUNCTION;

EID: 41749106247     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.903199     Document Type: Article
Times cited : (29)

References (20)
  • 1
    • 0028429228 scopus 로고
    • A comprehensive study of hot-carrier instability in p- and n-type poly-Si gated MOSFET's
    • May
    • C. C.-H. Hsu, D.-S. Wen, M. R. Wordeman, Y. Taur, and T. H. Ning, "A comprehensive study of hot-carrier instability in p- and n-type poly-Si gated MOSFET's," IEEE Trans. Electron Devices, vol. 41, no. 5, pp. 675-680, May 1994.
    • (1994) IEEE Trans. Electron Devices , vol.41 , Issue.5 , pp. 675-680
    • Hsu, C.C.-H.1    Wen, D.-S.2    Wordeman, M.R.3    Taur, Y.4    Ning, T.H.5
  • 2
    • 0024173315 scopus 로고
    • Mechanism of hot electron trapping on PMOSFET with p/sup+/polysilicon gate
    • I. Kato, H. Horie, M. Taguchi, and H. Ishikawa, "Mechanism of hot electron trapping on PMOSFET with p/sup+/polysilicon gate," in IEDM Tech. Dig., 1988, pp. 14-17.
    • (1988) IEDM Tech. Dig , pp. 14-17
    • Kato, I.1    Horie, H.2    Taguchi, M.3    Ishikawa, H.4
  • 3
    • 84949755257 scopus 로고    scopus 로고
    • N-channel versus p-channel flash EEPROM - Which one has better reliabilities
    • S. S. Chung et al., "N-channel versus p-channel flash EEPROM - Which one has better reliabilities," in Proc. 39th IEEE Reliab. Phys. Symp., 2001, pp. 67-72.
    • (2001) Proc. 39th IEEE Reliab. Phys. Symp , pp. 67-72
    • Chung, S.S.1
  • 6
    • 33847729042 scopus 로고    scopus 로고
    • Charge retention of silicided and unsilicided floating gates in embedded logic nonvolatile memory
    • B. Wang, H. Nguyen, A. Horch, Y. Ma, and R. Paulsen, "Charge retention of silicided and unsilicided floating gates in embedded logic nonvolatile memory," in Proc. Integr Reliab. Workshop Final Report 2005, pp. 67-70.
    • (2005) Proc. Integr Reliab. Workshop Final Report , pp. 67-70
    • Wang, B.1    Nguyen, H.2    Horch, A.3    Ma, Y.4    Paulsen, R.5
  • 7
    • 33751035214 scopus 로고    scopus 로고
    • Reliability and qualification of a floating gate memory manufactured in a generic logic process for RFID applications
    • Y. Ma, A. Pesavento, H. Nguyen, H. Li, and R. Paulsen, "Reliability and qualification of a floating gate memory manufactured in a generic logic process for RFID applications," in Proc. 21st Non-Volatile Semicond. Memory Workshop, 2006, pp. 44-45.
    • (2006) Proc. 21st Non-Volatile Semicond. Memory Workshop , pp. 44-45
    • Ma, Y.1    Pesavento, A.2    Nguyen, H.3    Li, H.4    Paulsen, R.5
  • 8
    • 0032202447 scopus 로고    scopus 로고
    • Polarity dependent gate tunneling currents in dual-gate CMOSFETs
    • Nov
    • Y. Shi, T. P. Ma, S. Prasad, and S. S. Dhanda, "Polarity dependent gate tunneling currents in dual-gate CMOSFETs," IEEE Trans. Electron Devices, vol. 45, no. 11, pp. 2355-2360, Nov. 1998.
    • (1998) IEEE Trans. Electron Devices , vol.45 , Issue.11 , pp. 2355-2360
    • Shi, Y.1    Ma, T.P.2    Prasad, S.3    Dhanda, S.S.4
  • 9
    • 0034583723 scopus 로고    scopus 로고
    • Analysis and implications of residual metal on spacer material in the self-align silicide process for VSLI manufacturing
    • P. L. Smith, T. Hossain, A. Ghatak-Roy, and J. Zhao, "Analysis and implications of residual metal on spacer material in the self-align silicide process for VSLI manufacturing," in Proc. 9th Symp. Semicond. Manuf., 2002, pp. 129-132.
    • (2002) Proc. 9th Symp. Semicond. Manuf , pp. 129-132
    • Smith, P.L.1    Hossain, T.2    Ghatak-Roy, A.3    Zhao, J.4
  • 11
    • 0028430427 scopus 로고
    • 2 breakdown model for very low voltage lifetime extrapolation
    • May
    • 2 breakdown model for very low voltage lifetime extrapolation," IEEE Trans. Electron Devices, vol. 41, no. 5, pp. 761-767, May 1994.
    • (1994) IEEE Trans. Electron Devices , vol.41 , Issue.5 , pp. 761-767
    • Schuegraf, K.F.1    Hu, C.2
  • 12
    • 33744905856 scopus 로고
    • Mechanism for stress-induced leakage currents in thin silicon dioxide films
    • Sep
    • D. J. DiMaria and E. Cartier, "Mechanism for stress-induced leakage currents in thin silicon dioxide films," J. Appl. Phys., vol. 78, no. 6, pp. 3883-3894, Sep. 1995.
    • (1995) J. Appl. Phys , vol.78 , Issue.6 , pp. 3883-3894
    • DiMaria, D.J.1    Cartier, E.2
  • 16
    • 0027811720 scopus 로고
    • Silicon dioxide breakdown life-time enhancement under bipolar bias conditions
    • Dec
    • E. Rosenbaum, Z. Liu, and C. Hu, "Silicon dioxide breakdown life-time enhancement under bipolar bias conditions," IEEE Trans. Electron Devices, vol. 40, no. 12, pp. 2287-2295, Dec. 1993.
    • (1993) IEEE Trans. Electron Devices , vol.40 , Issue.12 , pp. 2287-2295
    • Rosenbaum, E.1    Liu, Z.2    Hu, C.3
  • 20
    • 0033741528 scopus 로고    scopus 로고
    • Experimental evidence for voltage driven breakdown models in ultrathin gate oxides
    • P. E. Nicollian, W. R. Hunter, and J. C. Hu, "Experimental evidence for voltage driven breakdown models in ultrathin gate oxides," in Proc. 38th IEEE Reliab. Phys. Symp., 2000, pp. 7-15.
    • (2000) Proc. 38th IEEE Reliab. Phys. Symp , pp. 7-15
    • Nicollian, P.E.1    Hunter, W.R.2    Hu, J.C.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.