Scaling tunneling oxide to 50Å in floating-gate logic NVM at 65nm and beyond

IEEE International Integrated Reliability Workshop Final Report

Volumn , Issue , 2007, Pages 48-51

  Wang, Bin ^a   Niset, Martin ^a   Ma, Yanjun ^a   Nguyen, Hoc ^a   Paulsen, Ron ^a  

^a Impinj   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER CIRCUITS; DIGITAL STORAGE; RELIABILITY ANALYSIS;

FLOATING GATES; GATE OXIDE; HIGH RELIABILITY; LOGIC NVM; LOGIC PROCESS; PROCESS STEPS; SCALING LIMITS; SCALINGS; TUNNEL OXIDES; TUNNELING OXIDES;

GATE DIELECTRICS;

EID: 49649094561     PISSN: 19308841     EISSN: 23748036     Source Type: Conference Proceeding    
DOI: 10.1109/IRWS.2007.4469220     Document Type: Conference Paper

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