A 40 Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 11, 2008, Pages 2492-2502

  Liao, Chin Fan ^a   Liu, Shen Iuan ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

40 gb s receiver; Clock and data recovery; Equalizer; Serial link application

Indexed keywords

40 GB/S; 40-GB/S RECEIVER; 90NM CMOS; ADAPTIVE EQUALIZATIONS; ADAPTIVE EQUALIZERS; CDR CIRCUITS; CLOCK AND DATA RECOVERY; CLOCK JITTER; COPPER CABLES; FREQUENCY CONTENTS; HIGH FREQUENCIES; OUTPUT SWINGS; PHASE DETECTORS; POWER CONSUMPTIONS; RC FILTERS; SERIAL-LINK APPLICATION; SINGLE LOOPS;

ANALOG TO DIGITAL CONVERSION; CABLES; CMOS INTEGRATED CIRCUITS; COPPER; ELECTRIC FILTERS; JITTER; LOW PASS FILTERS; WAVE FILTERS;

HIGH PASS FILTERS;

EID: 56849109628     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2005535     Document Type: Article

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