-
1
-
-
0342484488
-
High-gain transimpedance amplifier in InP-based HBT technology for receiver in 40 Gb/s optical-fiber TDM links
-
Sep
-
J. Mullrich et al., "High-gain transimpedance amplifier in InP-based HBT technology for receiver in 40 Gb/s optical-fiber TDM links," IEEE J. Solid-State. Circuits, vol. 35, pp. 1260-1265, Sep. 2000.
-
(2000)
IEEE J. Solid-State. Circuits
, vol.35
, pp. 1260-1265
-
-
Mullrich, J.1
-
2
-
-
5444248069
-
6-kΩ 43 Gb/s differential transimpedance-limiting amplifier with autozero feedback and high dynamic range
-
Oct
-
H. Tran, F. Pera, D. S. McPherson, D. Viorel, and S. P. Voinigescu, "6-kΩ 43 Gb/s differential transimpedance-limiting amplifier with autozero feedback and high dynamic range," IEEE J. Solid-State Circuits, vol. 39, pp. 1680-1689, Oct. 2004.
-
(2004)
IEEE J. Solid-State Circuits
, vol.39
, pp. 1680-1689
-
-
Tran, H.1
Pera, F.2
McPherson, D.S.3
Viorel, D.4
Voinigescu, S.P.5
-
3
-
-
5444222183
-
An InGaAs-InP HBT differential transimpedance amplifier with 47 GHz bandwidth
-
Oct
-
J. S. Weiner et al., "An InGaAs-InP HBT differential transimpedance amplifier with 47 GHz bandwidth," IEEE J. Solid-State Circuits, vol. 39, pp. 1720-1723, Oct. 2004.
-
(2004)
IEEE J. Solid-State Circuits
, vol.39
, pp. 1720-1723
-
-
Weiner, J.S.1
-
4
-
-
0042781724
-
SiGe differential transimpedance amplifier with 50 GHz bandwidth
-
Sep
-
J. S. Weiner et al., "SiGe differential transimpedance amplifier with 50 GHz bandwidth," IEEE J. Solid-State. Circuits, vol. 38, pp. 1512-1517, Sep. 2003.
-
(2003)
IEEE J. Solid-State. Circuits
, vol.38
, pp. 1512-1517
-
-
Weiner, J.S.1
-
5
-
-
10444247327
-
40 Gb/s amplifier and ESD protection circuit in 0.18- μm CMOS technology
-
Dec
-
S. Galal and B. Razavi, "40 Gb/s amplifier and ESD protection circuit in 0.18- μm CMOS technology," IEEE J. Solid-State Circuits, vol. 39, pp. 2389-2396, Dec. 2004.
-
(2004)
IEEE J. Solid-State Circuits
, vol.39
, pp. 2389-2396
-
-
Galal, S.1
Razavi, B.2
-
6
-
-
2442671951
-
40 Gb/s CMOS distributed amplifier for fiber-optic communication systems
-
H. Shigematsu, M. Sato, T. Hirose, F. Brewer, and M. Rodwell, "40 Gb/s CMOS distributed amplifier for fiber-optic communication systems," in IEEE ISSCC Conf. Dig. Tech. Papers, 2004, pp. 476-477.
-
(2004)
IEEE ISSCC Conf. Dig. Tech. Papers
, pp. 476-477
-
-
Shigematsu, H.1
Sato, M.2
Hirose, T.3
Brewer, F.4
Rodwell, M.5
-
7
-
-
33845898890
-
A 40 Gb/s, digitally programmable peaking limiting amplifier with 20-dB differential gain in 90 nm CMOS
-
J. R. M. Weiss, M. L. Schmatz, and H. Jaeckel, "A 40 Gb/s, digitally programmable peaking limiting amplifier with 20-dB differential gain in 90 nm CMOS," in Proc. IEEE RFIC Symp., 2006.
-
(2006)
Proc. IEEE RFIC Symp
-
-
Weiss, J.R.M.1
Schmatz, M.L.2
Jaeckel, H.3
-
8
-
-
40149109812
-
40 Gb/s transimpedance amplifier in 0.18-μm CMOS technology
-
J.-D. Jin and S. S. H. Hsu, "40 Gb/s transimpedance amplifier in 0.18-μm CMOS technology," in Proc. ESSCIRC, 2006, pp. 520-523.
-
(2006)
Proc. ESSCIRC
, pp. 520-523
-
-
Jin, J.-D.1
Hsu, S.S.H.2
-
9
-
-
34548815262
-
40 Gb/s high-gain distributed amplifiers with cascaded gain stages in 0.18 μm CMOS
-
J.-C Chien and L.-H. Lu, "40 Gb/s high-gain distributed amplifiers with cascaded gain stages in 0.18 μm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 538-539.
-
(2007)
IEEE ISSCC Dig. Tech. Papers
, pp. 538-539
-
-
Chien, J.-C.1
Lu, L.-H.2
-
10
-
-
0346342381
-
A 40 Gb/s clock and data recovery circuit in 0.18-μm CMOS technology
-
Dec
-
J. Lee and B. Razavi, "A 40 Gb/s clock and data recovery circuit in 0.18-μm CMOS technology," IEEE J. Solid-State Circuits, vol. 38, pp. 2181-2190, Dec. 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, pp. 2181-2190
-
-
Lee, J.1
Razavi, B.2
-
11
-
-
3843106894
-
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with, a robust lock detector
-
Aug
-
H. Nosaka et al., "A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with, a robust lock detector," IEEE J. Solid-State Circuits, vol. 39, pp. 1361-1365, Aug. 2004.
-
(2004)
IEEE J. Solid-State Circuits
, vol.39
, pp. 1361-1365
-
-
Nosaka, H.1
-
12
-
-
33748365852
-
2.5 V 43-45 Gb/s CDR circuit and 55 Gb/s PRBS generator in SiGe using a low-voltage logic family
-
Sep
-
D. Kucharski and K. T. Kornegay, "2.5 V 43-45 Gb/s CDR circuit and 55 Gb/s PRBS generator in SiGe using a low-voltage logic family," IEEE J. Solid-State Circuits, vol. 41, pp. 2154-2165, Sep. 2006.
-
(2006)
IEEE J. Solid-State Circuits
, vol.41
, pp. 2154-2165
-
-
Kucharski, D.1
Kornegay, K.T.2
-
13
-
-
34347229830
-
A 40 Gb/s transimpedance-AGC amplifier with 19 dB DR in 90 nm CMOS
-
C.-F. Liao and S.-I. Liu, "A 40 Gb/s transimpedance-AGC amplifier with 19 dB DR in 90 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 54-55.
-
(2007)
IEEE ISSCC Dig. Tech. Papers
, pp. 54-55
-
-
Liao, C.-F.1
Liu, S.-I.2
-
14
-
-
14544300488
-
Jitter considerations in the design of a 10 Gb/s automatic gain control amplifier
-
Feb
-
D. Kucharski and K. T. Kornegay, "Jitter considerations in the design of a 10 Gb/s automatic gain control amplifier," IEEE Trans. Microwave Theory Tech., vol. 53, no. 2, pp. 590-597, Feb. 2005.
-
(2005)
IEEE Trans. Microwave Theory Tech
, vol.53
, Issue.2
, pp. 590-597
-
-
Kucharski, D.1
Kornegay, K.T.2
-
16
-
-
0346972289
-
10 Gb/s limiting amplifier and laser/modulator driver in 0.18- μm. CMOS technology
-
Dec
-
S. Galal and B. Razavi, "10 Gb/s limiting amplifier and laser/modulator driver in 0.18- μm. CMOS technology," IEEE J. Solid-State Circuits, vol. 38, pp. 2138-2146, Dec. 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, pp. 2138-2146
-
-
Galal, S.1
Razavi, B.2
-
17
-
-
0036503668
-
Capacity limits and matching properties of integrated capacitors
-
Mar
-
R. Aparicio and A. Hajimiri, "Capacity limits and matching properties of integrated capacitors," IEEE J. Solid-State Circuits, vol. 37, pp. 384-393, Mar. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, pp. 384-393
-
-
Aparicio, R.1
Hajimiri, A.2
-
18
-
-
0034430392
-
A low-phase noise CMOS LC oscillator with a ring structure
-
J. Kim and B. Kim, "A low-phase noise CMOS LC oscillator with a ring structure," in IEEE ISSCC Dig. Tech. Papers, 2000, pp. 430-431.
-
(2000)
IEEE ISSCC Dig. Tech. Papers
, pp. 430-431
-
-
Kim, J.1
Kim, B.2
-
19
-
-
23744483946
-
A 7-band 3-8 GHz frequency synthesizer with 1 ns band-switching time in. 0.18- μm CMOS technology
-
J. Lee and D.-W. Chiu, "A 7-band 3-8 GHz frequency synthesizer with 1 ns band-switching time in. 0.18- μm CMOS technology," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 204-205.
-
(2005)
IEEE ISSCC Dig. Tech. Papers
, pp. 204-205
-
-
Lee, J.1
Chiu, D.-W.2
-
20
-
-
0036917748
-
A 10 Gb/s CDR/DEMUX with LC delay line VCO in 0.18- μm CMOS
-
Dec
-
J. E. Rogers and J. R. Long, "A 10 Gb/s CDR/DEMUX with LC delay line VCO in 0.18- μm CMOS," IEEE J. Solid-State Circuits, vol. 37, pp. 1781-1789, Dec. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, pp. 1781-1789
-
-
Rogers, J.E.1
Long, J.R.2
-
21
-
-
0035507075
-
Rotary traveling-wave oscillator arrays: A new clock technology
-
Nov
-
J. Wood, T. C. Edwards, and S. Lipa, "Rotary traveling-wave oscillator arrays: A new clock technology," IEEE J. Solid-State Circuits, vol. 36, pp. 1654-1665, Nov. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, pp. 1654-1665
-
-
Wood, J.1
Edwards, T.C.2
Lipa, S.3
-
23
-
-
0016565959
-
Clock recovery from random binary data
-
Oct
-
J. D. H. Alexander, "Clock recovery from random binary data," Electron. Lett., vol. 11, pp. 541-542, Oct. 1975.
-
(1975)
Electron. Lett
, vol.11
, pp. 541-542
-
-
Alexander, J.D.H.1
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