A probabilistic method to determine the minimum leakage vector for combinational designs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 2241-2244

  Gulati, Kanupriya ^a   Jayakumar, Nikhil ^a   Khatri, Sunil P ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATIONAL DESIGN; LEAKAGE VECTOR; MINIMUM LEAKAGE STATE;

ELECTRIC POWER UTILIZATION; GATES (TRANSISTOR); HEURISTIC METHODS; LEAKAGE CURRENTS;

PROBABILISTIC LOGICS;

EID: 34547375207     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)

1. "BSIM3 Homepage." http://www-device.eecs.beriteley.edu/~bsim3/ arch_ftp.ht
2. "The International Technology Roadmap for Semiconductors." http://public.itrs.net/, 2003.
3. J. T. Kao and A. P. Chandrakasan, "Dual-threshold voltage techniques for low-power digital circuits," IEEE Journal of Solid-State Circuits, vol. 35, pp. 1009-1018, Jul 2000.
4. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-v power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE Journal of Solid-State Circuits, vol. 30, pp. 847-854, Aug 1995.
5. N. Jayakumar and S. Khatri, "An ASIC design methodology with predictably low leakage, using leakage-immune standard cells," in Proceedings of the International Symposium on Low Power Electronics and Design, pp. 128-133, Aug 2003.
6. H. Kawaguchi, K. Nose, and T. Sakurai, "A super cut-off CMOS (SC-CMOS) scheme for 0.5-v supply voltage with picoampere stand-by current," IEEE Journal of Solid-State Circuits, vol. 35, pp. 1498-1501, Oct 2000.
7. F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko, and C. Hu, "Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI," IEEE Transactions on Electron Devices, vol. 44, pp. 414-422, Mar 1997.
8. Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," in Proc. of IEEE Custom Integrated Circuit Conference, pp. 201-204, Jun 2000. http://www-device.eecs.berkeley.edu/ptm.
9. J. Halter and F. Najm, "A gate-level leakage power reduction method for ultra low power cmos circuits," in Proceedings of CICC, pp. 475-478, 1997.
10. Z. Chen, M. Johnson, L. Wei, and W. Roy, "Estimation of standby leakage power in CMOS circuit considering accurate modeling of transistor stacks," in International Symposium on Low Power Electronics and Design, pp. 239-244, 1998.
11. M. Johnson, D. Somasekhar, and K. Roy, "Models and algorithms for bounds on leakage in CMOS circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, pp. 714-725, June 1999.
12. F. Gao and J. Hayes, "Exact and heuristic approaches to input vector control for leakage power reduction," in Proceedings, International Conference on Computer-aided Design, pp. 527-532, Nov 2004.
13. K. Chopra and S. Vrudhula, "Implicit pseudo Boolean enumeration algorithms for input vector control," in Proceedings, Design Automation Conference, (San Diego), pp. 767-772, June 2004.
14. K. Gulati, N. Jayakumar, and S. Khatri, "An Algebraic Decision Diagram (ADD) based technique to find leakage histograms of combinational designs," in Proceedings, International Symposium on Low Power Electronic Design (ISLPED), (San Diego, CA), August 2005.
15. R. I. Bahar, E. A. Frohm, C. M. Gaona, G. D. Hachtel, E. Macii, A. Pardo, and F. Somenzi, "Algebraic decision diagrams and their applications," Formal Methods in Systems Design, vol. 10, no. 2/3, pp. 171-206, 1997.
16. R. Rao, F. Liu, J. Burns, and R. Brown, "A heuristic to determine low leakage sleep state vectors for CMOS combinational circuits," in Proceedings, International Conference on Computer-aided Design, pp. 689-692, Nov 2003.
17. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design. Computer Science Press, 1990.
18. F. Aloul, S. Hassoun, K. Sakallah, and D. Blauuw, "Robust SAT-based search algorithm for leakage power reduction," in Proceedings, Power and Timing Models and Simulation (PATMOS), 2002.
19. E. Goldberg and Y. Novikov, "BerkMin: A fast and robust SAT-solve," in Proceedings, Design Automation and Test in Europe (DATE) Conference, pp. 142-149, 2002.
20. S. Naidu and E. Jacobs, "Minimizing stand-by leakage power in static CMOS circuits," in Proceedings, Design Automation and Test in Europe (DATE) Conference, pp. 370-376, March 2001.