An object-aware hardware transactional memory system

Proceedings - 10th IEEE International Conference on High Performance Computing and Communications, HPCC 2008

Volumn , Issue , 2008, Pages 93-102

  Khan, Behram ^a   Horsnell, Matthew ^a   Rogers, Ian ^a   Luján, Mikel ^a   Dinn, Andrew ^a   Watson, Ian ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH PERFORMANCE LIQUID CHROMATOGRAPHY; MICROPROCESSOR CHIPS; PARALLEL PROGRAMMING; ROUTING ALGORITHMS;

BUS-BASED; CACHE COHERENCES; CONFLICT DETECTIONS; EXTENSIBLE SYSTEMS; HARDWARE TRANSACTIONAL MEMORIES; MANY CORES; MULTI-CORE SYSTEMS; OBJECT STRUCTURES; SOFTWARE IMPLEMENTATIONS; TRANSACTIONAL MEMORIES; VERSION MANAGEMENTS;

STORAGE ALLOCATION (COMPUTER);

EID: 56349122203     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCC.2008.110     Document Type: Conference Paper

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