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Volumn 25, Issue 5, 2008, Pages 430-439

Characterization of equalized and repeated interconnects for NoC applications

Author keywords

[No Author keywords available]

Indexed keywords

CHIP POWERS; INTER-CONNECTS;

EID: 55349118838     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2008.137     Document Type: Article
Times cited : (16)

References (12)
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    • R. Ho, On-Chip Wires: Scaling and Efficiency, doctoral dissertation, Dept. of Electrical Engineering, Stanford Univ., 2003.
    • R. Ho, "On-Chip Wires: Scaling and Efficiency," doctoral dissertation, Dept. of Electrical Engineering, Stanford Univ., 2003.
  • 4
    • 27844556591 scopus 로고    scopus 로고
    • Near Speed-of-Light On-Chip Interconnects Using Pulsed Current-Mode Signaling
    • IEEE Press
    • A.P. Jose, G. Patounakis, and K.L. Shepard, "Near Speed-of-Light On-Chip Interconnects Using Pulsed Current-Mode Signaling," Proc. IEEE Symp. VLSI Circuits, IEEE Press, 2005, pp. 108-111.
    • (2005) Proc. IEEE Symp. VLSI Circuits , pp. 108-111
    • Jose, A.P.1    Patounakis, G.2    Shepard, K.L.3
  • 5
    • 34548833578 scopus 로고    scopus 로고
    • A 0.28pJ/b 2Gb/s/ch Transceiver in 90 nm CMOS for 10 mm On-Chip Interconnects
    • IEEE Press
    • E. Mensink et al., "A 0.28pJ/b 2Gb/s/ch Transceiver in 90 nm CMOS for 10 mm On-Chip Interconnects," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 07), IEEE Press, 2007, pp. 414-415, 612.
    • (2007) Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 07)
    • Mensink, E.1
  • 6
    • 50249133214 scopus 로고    scopus 로고
    • Equalized Interconnects for On-Chip Networks: Modeling and Optimization Framework
    • IEEE Press
    • B. Kim and V. Stojanović, "Equalized Interconnects for On-Chip Networks: Modeling and Optimization Framework," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 07), IEEE Press, 2007, pp. 552-559.
    • (2007) Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 07) , pp. 552-559
    • Kim, B.1    Stojanović, V.2
  • 7
    • 36749031071 scopus 로고    scopus 로고
    • Flattened Butterfly Topology for On-Chip Networks
    • Feb
    • J. Kim, J. Balfour, and W.J. Dally, "Flattened Butterfly Topology for On-Chip Networks," IEEE Computer Architecture Letters, vol. 6, no. 2, Feb. 2007, pp. 37-40.
    • (2007) IEEE Computer Architecture Letters , vol.6 , Issue.2 , pp. 37-40
    • Kim, J.1    Balfour, J.2    Dally, W.J.3
  • 8
    • 0022061669 scopus 로고
    • Optimal Interconnection Circuits for VLSI
    • May
    • H.B. Bakoglu and J.D. Meindl, "Optimal Interconnection Circuits for VLSI," IEEE Trans. Electron Devices, vol. 32, no. 5, May 1985, pp. 903-909.
    • (1985) IEEE Trans. Electron Devices , vol.32 , Issue.5 , pp. 903-909
    • Bakoglu, H.B.1    Meindl, J.D.2
  • 9
    • 30844467759 scopus 로고    scopus 로고
    • Designing for Signal Integrity in Wave-Pipelined SoC Global Interconnects
    • IEEE Press
    • V. Deodhar and J.A. Davis, "Designing for Signal Integrity in Wave-Pipelined SoC Global Interconnects," Proc. IEEE Int'l SOC Conf. IEEE Press, 2005, pp. 207-210.
    • (2005) Proc. IEEE Int'l SOC Conf , pp. 207-210
    • Deodhar, V.1    Davis, J.A.2
  • 10
    • 0141426754 scopus 로고    scopus 로고
    • A 10-mW 3.6-Gbps I/O Transmitter
    • IEEE Press
    • H. Hatamkhani et al., "A 10-mW 3.6-Gbps I/O Transmitter," Proc. IEEE Symp. VLSI Circuits, IEEE Press, 2003, pp. 97-99.
    • (2003) Proc. IEEE Symp. VLSI Circuits , pp. 97-99
    • Hatamkhani, H.1
  • 11
    • 84886736952 scopus 로고    scopus 로고
    • New Generation of Predictive Technology Model for Sub-45nm Design Exploration
    • IEEE CS Press
    • W. Zhao and Y. Cao, "New Generation of Predictive Technology Model for Sub-45nm Design Exploration," Proc. IEEE Int'l Symp. Quality Electron Design (ISQED 06), IEEE CS Press, 2006, pp. 585-590.
    • (2006) Proc. IEEE Int'l Symp. Quality Electron Design (ISQED 06) , pp. 585-590
    • Zhao, W.1    Cao, Y.2
  • 12
    • 50249185641 scopus 로고    scopus 로고
    • A 45 nm Logic Technology with High-k+ Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193 nm Dry Patterning, and 100% Pb-Free Packaging
    • IEEE Press
    • K. Mistry et al., "A 45 nm Logic Technology with High-k+ Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193 nm Dry Patterning, and 100% Pb-Free Packaging," Proc. IEEE Int'l Electronic Devices Meeting (IEDM 07), IEEE Press, 2007, pp. 247-250.
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    • Mistry, K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.