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Volumn , Issue , 2005, Pages 207-210

Designing for signal integrity in wave-pipelined soc global interconnects

Author keywords

[No Author keywords available]

Indexed keywords

SIGNAL INTEGRITY; SYSTEM-ON-CHIP (SOC); WAVE-PIPELINED INTERCONNECTS;

EID: 30844467759     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (1)

References (10)
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    • V. Deodhar and J. Davis, "Optimization of throughput performance for low-power VLSI interconnects," IEEE Trans. VLSI Systems, vol. 13, no. 3, pp. 308-318, Mar. 2005.
    • (2005) IEEE Trans. VLSI Systems , vol.13 , Issue.3 , pp. 308-318
    • Deodhar, V.1    Davis, J.2
  • 4
    • 0032276826 scopus 로고    scopus 로고
    • A high performance 180 nm generation logic technology
    • S. Yang et al., "A high performance 180 nm generation logic technology," in Proc. Int Electron Devices Meeting (IEDM), 1998, pp. 197-200.
    • (1998) Proc. Int Electron Devices Meeting (IEDM) , pp. 197-200
    • Yang, S.1
  • 5
    • 0022061669 scopus 로고
    • Optimal interconnection circuits for VLSI
    • May
    • H. Bakoglu and J. Meindl, "Optimal interconnection circuits for VLSI," IEEE Trans. Electron Devices, vol. ED-32, no.5, pp. 903-909, May 1985.
    • (1985) IEEE Trans. Electron Devices , vol.ED-32 , Issue.5 , pp. 903-909
    • Bakoglu, H.1    Meindl, J.2
  • 7
    • 0035704586 scopus 로고    scopus 로고
    • Optimal ntier multilevel interconnect architectures for gigascale integration (GSI)
    • Dec.
    • R. Venkatesan, J. Davis, K. Bowman and J. Meindl, "Optimal ntier multilevel interconnect architectures for gigascale integration (GSI)," IEEE Trans. VLSI Systems, vol. 9, no. 6, Dec. 2001.
    • (2001) IEEE Trans. VLSI Systems , vol.9 , Issue.6
    • Venkatesan, R.1    Davis, J.2    Bowman, K.3    Meindl, J.4
  • 8
    • 84858518105 scopus 로고    scopus 로고
    • The MOSIS Service. (Online)
    • The MOSIS Service. (Online). Available: http://www.mosis.org
  • 9
    • 84944072550 scopus 로고    scopus 로고
    • A wave-pipelined on-chip interconnect structure for networks-on-chips
    • J. Xu and W. Wolf, "A wave-pipelined on-chip interconnect structure for networks-on-chips," in Proc. High Perf. Interconnects (HOTI), 2003, pp. 10-14.
    • (2003) Proc. High Perf. Interconnects (HOTI) , pp. 10-14
    • Xu, J.1    Wolf, W.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.