A 10-mW 3.6-Gbps I/O Transmitter

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2003, Pages 97-98

  Hatamkhani, Hamid ^a   Wong, Koon Lun Jackie ^a   Drost, Robert ^b   Yang, Chih Kong Ken ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; ELECTRIC LOSSES; ELECTRIC POWER UTILIZATION; IMPEDANCE MATCHING (ELECTRIC);

CHANNEL EQUALIZATION;

TRANSMITTERS;

EID: 0141426754     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. M.-J. E. Lee, W. J. Dally, and P. Chiang, "Low-power, area efficient, high speed I/O circuit techniques," IEEE J. Solid-State Circuits, vol. 35, pp. 1591-1599, Nov. 2000.
2. F. Yang, J. H. O'Neill, D. Inglis, and J. Othmer, "A CMOS low-power multiple 2.5-3.125-Gb/s serial link macrocell for high 10 bandwidth network" IEEE J. Solid-State Circuits, vol. 37, pp. 1813-1821, Dec. 2002.