A novel SCR ESD protection structure with low-loading and Latchup immunity for high-speed I/O pad

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn 2003-January, Issue , 2003, Pages 80-83

  Lai, Chen Shang ^a   Liu, Meng Hwang ^a   Su, Shin ^a   Lu, Tao Cheng ^a  

^a MXIC   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTROSTATIC DISCHARGE;

CONTROL CIRCUITS; DISCHARGING PATHS; ESD PROTECTION; ESD PROTECTION DEVICES; GATE-COUPLE; HIGH SPEED I/O; NORMAL OPERATIONS; TRIGGER VOLTAGE;

ELECTROSTATIC DEVICES;

EID: 5444235583     PISSN: 19308868     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2003.1252557     Document Type: Conference Paper

References (6)

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2. Ajith Amerasekera, Charvaka Duwury, ESD In Silicon Integrated Circuits, p. 63-p. 69, Dallas: Wiley, 1995.
3. Ajith Amerasekera, Charvaka Duvvury, ESD In Silicon Integrated Circuits, p. 182-p. 186, Dallas: Wiley, 1995.
4. th EOS/ESD Symposium, p. 177-180, 1983.
5. A. Chatterjee, T. Polgreen, "A Low Voltage Triggering SCR for On-Chip ESD Protection at Output and Intput Pads", IEEE Elec. Dev. Lett., EDL-12, p. 21-22, 1991.
6. J. Barth, K. Verhaege, L. G. Henry, J. Richner, "TLP Calibration, Correlation, Standards, and New Techniques", Proceedings of the EOS-ESD symposium, p. 85-p. 96, 2000.