Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protection

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1998, Pages 541-544

  Ker, Ming Dou ^a   Chang, Hun Hsien ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC DISCHARGES; ELECTROSTATICS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; SPURIOUS SIGNAL NOISE; TUNING;

ELECTROSTATIC DISCHARGES (ESD);

THYRISTORS;

EID: 0031620160     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)