Compact and power-efficient implementation of rank-order filters using time-domain digital computation technique

Japanese Journal of Applied Physics

Volumn 47, Issue 4 PART 2, 2008, Pages 2807-2811

  Nguyen, Liem T ^a   Ito, Kiyoto ^a   Shibata, Tadashi ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

Hardware implementation; Median filter; Parallel processing; Rank order filter; Time domain computation; VLSI

Indexed keywords

ADDERS; ANALOG TO DIGITAL CONVERSION; CHARGE COUPLED DEVICES; DIGITAL ARITHMETIC; DIGITAL TO ANALOG CONVERSION; HARDWARE; IMAGE PROCESSING; LOGIC CIRCUITS; METALLIC COMPOUNDS; MODULATION; MOS DEVICES; POWDERS; SEMICONDUCTOR MATERIALS; TIME DOMAIN ANALYSIS; WAVE FILTERS;

HARDWARE IMPLEMENTATION; MEDIAN FILTER; PARALLEL PROCESSING; RANK-ORDER FILTER; TIME-DOMAIN COMPUTATION; VLSI;

DIGITAL FILTERS;

EID: 54249087586     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.47.2807     Document Type: Article

References (26)

1. J. W. Tukey: Congr. Rec. EASCON, 1974, p. 673.
2. P. D. Wendt, E. J. Coyle, and N. C. Gallagher, Jr.: IEEE Trans. Acoust. Speech Signal Process. 34 (1986) 898.
3. D. S. Richard: IEEE Trans. Acoust. Speech Signal Process. 38 (1990) 145.
4. L. R. Rabiner, M. R. Sambur, and C. E. Schmidt: IEEE Trans. Acoust. Speech Signal Process. 23 (1975) 552.
5. T. Shibata: Proc. IEEE Int. Symp. Intelligent Signal Processing and Systems, 2000, p. 323.
6. A. C. Bovik, T. S. Huang, and D. C. Munson, Jr.: IEEE Trans. Pattern Anal. Mach. Intell. 9 (1987) 181.
7. H. Yamasaki and T. Shibata: IEEE J. Solid-State Circuits 42 (2007) 2046.
8. G. R. Arce and N. C. Gallagher, Jr.; IEEE Trans. Commun. 31 (1983) 784.
9. E. R. Ritenour, T. R. Nelson, and U. Raff: Proc. IEEE Int. Conf. Acoustics, Speech and Signal Processing, 1984, p. 251.
10. M. Karaman, L. Onural, and A. Atalar: IEEE J. Solid-Stale Circuits 25 (1990) 505.
11. C. C. Lin and C. J. Kuo: IEEE Trans. Circuits Syst. Video Technol. 8 (1998) 941.
12. L. Breveglieri and V. Piuri: J. VLSI Signal Process. 31 (2002) 191.
13. B. K. Kar and D. K. Pradhan: IEEE Trans. Signal Process. 41 (1993) 2688.
14. A. A. Hiasat, M. M. Al-Tbrahim, and K. M. Gharaibeh: Proc. TEE Vision, Image and Signal Processing, 1999, p. 273.
15. V. A. Pedroni: Proc. IEEE Int. Symp. Circuits and Systems, 2004, p. 11-585.
16. L. R. Dung and M. C. Lin: IEEE Trans. Consum. Electron. 50 (2004) 558.
17. C. L. Lee and C. W. Jen: IEE Proc. - Circuits Devices Syst. 139 (1992) 63.
18. H. Yamasaki and T. Shibata: Proc. 31 st European Solid-State Circuits Conf., 2005, p. 125.
19. C. D. Thompson, H. Yasuura, and U. C. Berkeley: Proc. IEEE 19th Asilomar Conf. Circuits, Systems and Computers, 1985, p. 365.
20. A. Iwata and M. Nagata: IEICE Trans. Fundam. E79-A (1996) 145.
21. M. Nagata and A. Iwata: IEEE J. Solid-State Circuits 33 (1998) 53.
22. K. Ito and T. Shibata: Proc. IEEE Int. Symp. Circuits and Systems, 2006, p. 201.
23. K. Ito and T. Shibata: Proc. Int. Symp. System-on-Chip, 2007, p. 23.
24. J. Ramirez-Angulo, R. Gonzalez-Carvajal, G. O. Ducoudray, A. J. Lopez-Martin, and A. Torralba: IEEE Trans. Circuits Syst. II 51 (2004) 257.
25. B. P. Tan and D. M. Wilson: IEEE Trans. Circuits Syst. II 48 (2001) 198.
26. U. Cilingiroglu and L. E. Dake: IEEE J. Solid-Stale Circuits 37 (2002) 978.