A high-speed median filter VLSI using floating-gate-MOS-based low-power majority voting circuits

Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference

Volumn , Issue , 2005, Pages 125-128

  Yamasaki, Hideo ^a   Shibata, Tadashi ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ENERGY UTILIZATION; LOW PASS FILTERS; MICROPROCESSOR CHIPS; MOS CAPACITORS;

FLOATING GATES; LATENCY SEARCH; VOTING CIRCUITS;

VLSI CIRCUITS;

EID: 33749182177     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.2005.1541575     Document Type: Conference Paper

References (6)

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2. R. Roncella, R. Saletti, and P.Terreni, "70-MHz 2-μm CMOS Bit-Level Systolic Array Median Filter," IEEE J. Solid-State Circuits, vol. 28, pp. 530-536, May 1993.
3. D.-L. Yang and C.-H. Chen, "Data Dependence Analysis and Bit-Level Systolic Arrays of the Median Filler," IEEE Trans. Circuits Syst. Video Technol., vol. 8, pp. 1015-1024, Dec. 1998.
4. B.L. Lee and C.-W. Jen, "Bit-sliced median filter design based on majority gate," IEE Proceedings-G, vol. 139, pp. 63-71, Feb. 1992.
5. M. Yagi, H. Yamasaki, and T. Shibata, "A Mixed-Signal VLSI for Real-Time Generation of Edge-Based Image Vectors," Proc. NIPS, pp. 1035-1042, Dec. 2003.
6. H. Yamasaki and T. Shibata, "A Real-Time VLSI Median Filter Employing Two-Dimensional Bit-Propagating Architecture," Proc. ISCAS, pp. II-349-352, May 2004.