A 40-44 Gb/s 3 × oversampling CMOS CDR/1:16 DEMUX

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 12, 2007, Pages 2726-2735

  Nedovic, Nikola ^a   Tzartzanis, Nestoras ^a   Tamura, Hirotaka ^b   Rotella, Francis M ^a   Wiklund, Magnus ^a   Mizutani, Yuma ^c   Okaniwa, Yusuke ^c   Kuroda, Tadahiro ^c   Ogawa, Junji ^b   Walker, William W ^a  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

^b FUJITSU LABORATORIES LTD   (Japan)

^c KEIO UNIVERSITY   (Japan)

Author keywords

Clock and data recovery (CDR); CML; CMOS; Delay line; Demultiplexer; Distributed circuits; Distributed VCO; Hybrid CDR; Jitter tolerance; Optical communications; Oversam pling; Serializer deserializer

Indexed keywords

CLOCK AND DATA RECOVERY; CML; CMOS; DELAY LINE; DEMULTIPLEXERS; DISTRIBUTED CIRCUITS; DISTRIBUTED VCO; HYBRID CDR; JITTER TOLERANCE; OVERSAM-PLING; SERIALIZERS;

CLOCKS; CMOS INTEGRATED CIRCUITS; DEMULTIPLEXING; OPTICAL COMMUNICATION; TIMING JITTER; VARIABLE FREQUENCY OSCILLATORS; WAVES;

DELAY CIRCUITS;

EID: 53949105775     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.908714     Document Type: Conference Paper

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