Integrated power-gating and state assignment for low power FSM synthesis

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008

Volumn , Issue , 2008, Pages 269-274

  Pradhan, Sambhu Nath ^a   Kumar, M Tilak ^a   Chattopadhyay, Santanu ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY   (India)

Author keywords

FSM decomposition; Genetic algorithm; Low power synthesis; Power gating; State encoding

Indexed keywords

ENCODING (SYMBOLS); LEAKAGE CURRENTS; STATE ASSIGNMENT; TECHNOLOGY;

ALGORITHMIC APPROACH; AREA PENALTY; DYNAMIC POWER; FINITE STATE MACHINE; FSM DECOMPOSITION; GENETIC ALGORITHM; INTEGRATED POWER; LOGIC BLOCKS; LOW POWER SYNTHESIS; LOW POWERS; POWER SAVINGS; POWER SUPPLIES; POWER-GATING; STAND-BY LEAKAGE; STATE ENCODING; VLSI TECHNOLOGIES;

ENERGY CONSERVATION;

EID: 51849140901     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2008.7     Document Type: Conference Paper

References (22)

1. F. Najm, "A survey of Power Estimation Techniques in VLSI Circuits "(invited paper), IEEE Transation on VLSI Systems, 2(4):446-455, December 1994.
2. S. Chattopadhyay, "Low power state assignment and flip-flop selection for finite state machine synthesis- A Genetic Algorithm Approach," IEE proceedings on Computer and Digital Techniques vol.125, no. 4/5, pp. 124-151, July 2001.
3. L. Benini and G. De Micheli, "State Assignment for Low Power Dissipation," IEEE journal on Solid State Circuits, pp.32-40, March 1994.
4. W. Noeth, R. Kolla. "Spanning Tree-based State Encoding for Low Power Dissipation," Design Automation and Test in Europe, March 1999.
5. Roy K., and S. Preasad, "SYCLOP Synthesis of CMOS Logic for Low Power Applications,". ICCD'92, pp.234-237, 1992.
6. S. Devadas, H. K.T. Ma, A. R. Newton, and A.S. Vincentelli , Mustang: "State Assignment of Finite State Machines for Optimal Multilevel Logic Implementation," IEEE Transaction on Computer Aided Design, vol.7, No. 12, pp.1290-1300, December 1998.
7. Y. Xia and A. E. A. Almaini, "Genetic Algorithm based State Assignment for power and Area Optimization.," IEE proceedings on Computer and Digital Techniques, vol. 126, no.4, pp.128-133, July 2002.
8. C. Y. Tsui, M. Pedram, C.A. Chen, A. M. Despain, " Low Power State Assignment targetting Two- and Multilevel Logic Implementation," ICCAD, pp. 82-87, 1994.
9. P. Surti, L.F. Chao, A. Tyagi, "Low Power FSM Design using Huffman-style Encoding," IEEE EDTC-97,Paris, France, pp.521-525, March 1997.
10. R. K. Brayton, G. D. Hachtel, C. T. McMullen, and A. L. Sangiovanni-Vincentelli, Logic minimization algorithms for VLSI synthesis, Kluwer Academic, 1985.
11. A. Iranli, P. Rezvani, M. Pedram, " Low Power Synthesis of Finite State Machines with Mixed D and T Flip-Flops," IEEE 2003.
12. th IEEE conf. on VLSI design 2003.
13. S. Chattopadhyay and P. N, Reddy, "Finite state machine state assignment targeting low power consumption," IEE Proceedings on Computer and Digital Techniques, vol.151, No.1, Jan.2004.
14. Gustavo Sutter, Elias Todorovich, Sergio Lopez-Buedo, and Eduardo Boemo, FSM Decomposition for Low Power in FPGA.
15. H. Lensen, M. Kruus, A. Sudnitson, "Synthesis of Sequential Circuits with Dynamic Power management," RTUCET'01, Riga, Latvia, 2001, p.81-86.
16. S.H. Chow, Y.C. Ho, T. Hwang and C.L. Liu, "Low power realization of finite state machines-a decomposition approach," ACM Trans. Design Automat. Elect. Syst., vol.1, no.3, pp.315-340, July 1996.
17. J. C. Monteiro, A. L. Oliveira, "Finite State machine Decomposition for Low Power," DAC 98, pp. 758-763.
18. st Century. Intel Technology Journal, Q3,1998.
19. B. Liu, Y. Cai, Q. Zhou, J. Bian, X. Hong, "FSM decomposition for power gating design automation in sequential circuits," pp. 862-865, ASICON 2005.
20. D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning .
21. www.eecs.berkeley.edu/Pubs/TechRpts/1992/2010.html.
22. T. Villa, A. S. Vincentell, "NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementation," IEEE transactions on CAD. VOL. 9 NO. 9. September 1990, pp. 905-924.